Deglitch method and apparatus to assure valid data sampling

Details Deglitch method and apparatus to assure valid data sampling Deglitch method and apparatus to assure valid data sampling

1997-08-22

1998-09-29

Butler, Dennis M.

Boots, shoes, and leggings

395555, 364574, G06F 104

Patent

active

058156909

ABSTRACT:
A deglitch circuit for filtering false transitions of an input signal based on transitions of a clock signal. A plurality of memory devices as provided for detecting the input signal being assay for two, three and five transitions of the clock signal in the preferred embodiment. Programmable select logic is also provided for selecting between these three cases. In the preferred embodiment, six separate flip-flops are included and clocked by the clocked signal, four of the flip-flops being reset upon spurious negations of the input signal for reign such transitions, and where two of the four flip-flops are clocked on the rising edge whereas the other two are clocked on the falling edge of the clock signal. The programmable select logic preferably includes a multiplexer for choosing between the three cases. In the preferred embodiment, the input signal is the data valid (DAV) signal of a GPIB, where the deglitch circuit assures valid data sampling on a GPIB.

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1994 IEEE 488 and VXIbus Control, Data Acquisition, and Analysis, National Instruments Corporation, "GPIB Monitor/Analyzer, GPIB-410," 2-126-2-129, High Performance Single-Chip GPIB Talker/Listener ASIC, TNT4882, pp. 2-135-2-136.
Iotech Smart Approach to Instrumentation 1993 Catalog, National Instruments Corporation, "Analyzer 488, IEEE Bus Analyzer," pp. 51-54 and pp. 37-41.
1993-1994 ICS Electronics Corporation Catalog, "IEEE 488/GPIB Bus Analyzer With Multiline Display," pp. 7-1-7-6, 4811 Bus Analyzer With Multiline Display, 6 pages (not numbered).
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