Patent
1997-01-29
1998-07-07
MacDonald, Allen R.
395 61, 395900, G06G 700
Patent
active
057781494
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a defuzzification device in a fuzzy logic circuit.
2. Description of the Related Art
In fuzzy logic controllers with a resolution greater than 8 bits, it is expedient to store and to process the membership functions of linguistic variables in the form of measurement figures which characterize these membership functions. Therefore, defuzzification devices are also needed which form a sharp output value from aggregated regulation weights formed in an inference unit and from measurement figures for the membership functions of the linguistic output variables. Since there is a plurality of different defuzzification processes and at least the most important of these processes are intended to be optionally possible, in order to be able to achieve the most optimum regulation/classification results, this leads to a correspondingly high chip area requirement.
SUMMARY OF THE INVENTION
An object on which the invention is based is to provide a defuzzification device which is as fast as possible and has the smallest possible chip area, and with which the most important defuzzification processes may be carried out.
This and other objects of the invention are achieved by a defuzzification device for a fuzzy logic controller which processes membership functions in the form of measurement figures, in which, depending on selection signals and aggregated regulation weights, either in a maximum process a first maximum value of the fuzzy unification set to be defuzzified, at which an associated aggregated regulation weight is a maximum, or a last maximum value of the fuzzy unification set to be defuzzified, at which an associated regulation weight is a maximum, is selected as the sharp output value and a corresponding activation signal for a knowledge base memory interface is formed or, alternatively, depending on selection signals, a sharp output value is formed either in a first center of gravity process , from center of gravity coordinates and aggregated regulation weights of membership functions or in a second center of gravity process from center of gravity coordinates, area measurement figures and aggregated regulation weights, in which a first adder with downstream counter register, a second adder with downstream denominator register, a multiplier and a divider are provided jointly for the first and second center of gravity process, and in which the second adder is used to form the activation signal if defuzzification is being carried out according to the maximum process.
Preferred embodiments of the device according to the invention, provide that a signal for discriminating between a defuzzification according to the first or second center of gravity process is carried out in that all the area measurement figures are encoded with zero in the case of the first center of gravity process and by a corresponding discrimination signal being formed by means of a NOR operation on the bits of the respective area measurement figure. computing time is being saved by no multiplication being carried out if the respective area measurement figure is equal to zero or equal to one.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be explained below in greater detail using the drawings, in which
FIG. 1 is a block diagram of a high-resolution fuzzy logic controller having a defuzzification device according to the invention,
FIG. 2 is a circuit diagram of a defuzzification device according to the invention,
FIG. 3A is a first part of a flow diagram to explain the control signals of a defuzzification device according to the invention,
FIG. 3B is a second part of a flow diagram to explain the control signals of a defuzzification device according to the invention,
FIG. 4 schematic diagram and a table which; shows a representation to explain the allocation of the knowledge base memory as a function of the defuzzification process selected, and
FIG. 5 is a diagram of a part of the knowledge base memory interface to explain the significance
REFERENCES:
patent: 5459816 (1995-10-01), Basehore et al.
patent: 5524174 (1996-06-01), Eichfeld et al.
patent: 5600757 (1997-02-01), Yamamoto et al.
H. Hellendoorn, "Design And Development Of Fuzzy Systems At Siemens R&D", Second IEEE International Conference on Fuzzy Systems, California, 1993, pp. 1365-1370.
K. Goser et al., "Clevere Regler schnell entworfen", Automatisieren Fuzzy-Logik, Elektronik Jun. 1992.
MacDonald Allen R.
Rhodes Jason W.
Siemens Aktiengesellschaft
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