Abrading – Abrading process – Glass or stone abrading
Reexamination Certificate
2000-07-17
2003-12-23
Kunemund, Robert (Department: 1765)
Abrading
Abrading process
Glass or stone abrading
C451S285000, C451S287000, C451S288000, C451S533000, C451S526000
Reexamination Certificate
active
06666751
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to methods for forming a uniform layer of material on a substrate, such as a semiconductor wafer. More particularly, the invention relates to a polishing pad for chemical mechanical polishing (CMP), a polishing apparatus, and methods for using the same.
2. State of the Art
In the fabrication of semiconductor devices, it is often necessary to planarize or polish material layers of an intermediate semiconductor structure before the intermediate device may be subjected to further process steps, such as, for example, deposition, patterning, or etching steps. Planarization is used to achieve material layers of uniform thickness and to remove undesirable surface topography, scratches, roughness, embedded particles, or other defects which may adversely effect the consistency or effectiveness of subsequent process steps. One of the most widely utilized planarization processes is CMP.
CMP is an abrasive planarization process which generally involves agitating a material layer to be polished against a wetted polishing surface under controlled chemical, pressure, and temperature conditions.
FIG. 1A
shows an exemplary CMP apparatus
10
having a rotatable platen, or table
12
, and a polishing pad
14
mounted to a top surface
16
of the rotatable table
12
. A carrier film (not illustrated in
FIG. 1A
) may also be placed between the polishing pad
14
and the top surface
16
of the rotatable table
12
to protect the top surface
16
of the rotatable table
12
. Such a film may be provided to protect the top surface
16
of the rotatable table
12
from scratches and chemical degradation or contamination.
The CMP apparatus of
FIG. 1A
also includes a rotatable substrate carrier
18
configured to hold a semiconductor substrate
20
(such as, by way of example, a silicon wafer) bearing a material layer
25
to be polished. The substrate carrier
18
exerts a downward force, indicated by arrow
22
, normal to the surface
24
of the material layer
25
to be polished, creating a pressure between the surface
24
of the material layer
25
to be polished and the polishing surface
26
of the polishing pad
14
. The rotatable substrate carrier
18
may be designed to exert varying amounts of force against the semiconductor substrate
20
and may utilize various, well-known technologies, such as mechanical affixation, vacuum affixation, frictional affixation, or any other suitable technique, to hold the semiconductor substrate
20
in place during polishing.
As is also shown in
FIG. 1A
, both the rotatable substrate carrier
18
and the rotatable table
12
may be rotated or otherwise placed in motion to provide the agitation necessary for polishing. The rotatable table
12
is rotated in a first direction
28
by a first known mechanical assembly
30
, such as, for example, a first electric motor. The rotatable substrate carrier
18
may be rotated in a second direction
32
by a second known mechanical assembly
34
, such as, for example, a second electric motor. The second direction
32
may be the same rotational direction as the first direction
28
. Moreover, the substrate carrier
18
may provide further agitation through movement in a plane, indicated by arrow
36
, parallel to the top surface
16
of the rotatable table
12
.
FIG. 1B
illustrates an alternative CMP apparatus that does not employ a rotatable platen. Instead, the CMP apparatus of
FIG. 1B
includes a linear polisher
2
and a substrate carrier
3
for holding the substrate
4
to be polished. The linear polisher
2
includes an endless belt
5
, which is movable in a continuous path and is supported by a belt support
6
. A polishing pad
7
is attached to the endless belt
5
, and the polishing pad
7
is positioned to engage the substrate surface
8
. The polishing pad
7
is moved in a linear direction relative to the substrate
4
, and in order for polishing to occur at random incidence, the substrate carrier
3
preferably rotates the substrate
4
relative to the polishing pad
7
affixed to the endless belt
5
. CMP machinery including linear polishing mechanisms are currently thought to provide improved polishing relative to machinery utilizing rotatable polishing tables.
Regardless of the machinery used, as is illustrated in
FIG. 1A
, a wetting agent
38
, generally a chemical slurry
40
, is often supplied through a conduit
42
and onto the polishing surface
26
of the polishing pad
14
. The wetting agent
38
generally contains a polishing agent, such as alumina, silica, or fused silica, carried in an ammonium hydroxide solution or the like, which serves as an abrasive material. Additionally, the wetting agent
38
may contain other chemicals which selectively etch or degrade particular features of the material layer
25
to be polished. However, as the dimensions of features included in state of the art semiconductor devices shrink, chemically active slurries have fallen out of favor in some CMP applications, as it is very difficult to control the etch rate of chemically active constituents during a CMP process. Therefore, as used in the context of the present invention, the terms “chemical mechanical polishing” and “CMP” indicate abrasive polishing processes that employ chemically inert slurries, as well as polishing processes employing chemically active slurries.
The effect of CMP is illustrated in
FIGS. 2 through 4
. Each of these figures illustrate an incomplete semiconductor device
44
before or after undergoing CMP. However, the application of CMP processes is not limited to incomplete semiconductor devices having the characteristics illustrated in
FIGS. 2 through 4
. As is well-known by those of ordinary skill in the art, CMP processes may be applied to a wide range of semiconductor devices at various stages of fabrication. Moreover, as is also well-known, CMP process parameters are variable, depending on the desired result and the characteristics of the substrate being polished. The structures and results depicted in
FIGS. 2 through 4
are therefore provided for illustrative purposes only.
FIG. 2
depicts an incomplete semiconductor device
44
including a portion of a semiconductor substrate
46
, such as a wafer, a lower wiring layer
48
, and a material layer
50
, such as an interlayer dielectric film
50
. Due to the topography created by the lower wiring layer
48
, the upper surface
52
of the material layer
50
is irregular, including a plurality of peaks
54
and valleys
56
. Before further processing occurs, however, it is desirable to eliminate the peaks
54
and valleys
56
, creating a material layer having a planar surface and a uniform thickness (not shown in FIG.
2
).
FIG. 3
illustrates the incomplete semiconductor device
44
of
FIG. 2
after the incomplete semiconductor device
44
has undergone a desirable CMP process. Ideally, the CMP process results in a uniformly thick material layer
58
with a planar top surface
60
, enabling subsequent process steps that consistently produce reliable device features. However, nonuniformity of polishing rate is a serious problem inherent in known CMP processes, and consistently achieving material layers having planar top surfaces and a uniform thickness across the entire surface of the material layer being polished has proven difficult.
FIG. 4
illustrates the incomplete semiconductor device
44
of
FIG. 2
following a more typical CMP process. At least in some areas of the polished surface, the nonuniform polishing rate of a typical CMP process results in an incomplete semiconductor device
44
having a nonuniform material layer
62
and a top surface
64
that slopes (greatly exaggerated for clarity) or is otherwise irregular. It must be emphasized, however, that
FIG. 4
depicts only one type of irregularity caused by known CMP processes. The results obtained by any CMP process will depend on the material being polished, the unique characteristics of the features formed by the material being polished, and numerous process paramete
Kunemund Robert
Micro)n Technology, Inc.
TraskBritt
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