Definition of physical level of a logic output by a logic input

Details Definition of physical level of a logic output by a logic input Definition of physical level of a logic output by a logic input

2000-03-20

2002-04-23

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S122000

Reexamination Certificate

active

06377198

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
The subject matter of the present application is related to that in U.S. patent application Ser. No. 09/466,835, filed Dec. 20, 1999, entitled “Techniques for Improving Signal to Noise Ratio in a Digital Filter using Spread Zeros” (Nanda), and U.S. patent application Ser. No. 09/521,675 filed concurrently herewith, entitled “Single Wire Interface for Analog-to-digital Converter” (Pastorello et al.) both of which are incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to the field of semiconductor devices. In particular, the present invention relates to an apparatus for controlling the voltage level of a logic output in relation to the logic input voltage level.
BACKGROUND OF THE INVENTION
For a chip working in a multiple supply environment, the physical voltage level of an output pin may be different from every supply to the chip. For example, an analog-to-digital converter may be supplied by a so-called dual supply power supply with a V+of +3 Volts and a V− of −2 Volts. Alternately, other supply voltages may be used, such as a V+ of +5 Volts and a V− of 0 Volts.
Digital signal levels within such circuitry may have voltage levels different than supply voltage levels. Thus, in the examples given above, a high logic level may be 3 Volts and a low logic level may be 0 Volts. Logic level voltages may or may not correspond to input supply voltages.
As a result, there is no simple technique for generating appropriate and consistent voltage levels for output digital signals on such a chip. In addition, if a chip is designed to work with various voltage supply levels, generating consistent and accurate logic level signals relative to supply voltage levels may be somewhat difficult.
One intuitive approach to solving these problems is to provide an additional input reference voltage signal or signals through a corresponding separate input pin or pins representing one or more logic levels. However, such an approach requires one or more extra input pins for such reference voltage signals.
In semiconductor chip design, it is desirable to reduce the number of input, output, or voltage supply pins in order to reduce package size and reduce cost. Thus, using an additional pin or pins for reference voltage signals may not be an acceptable solution.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus to define and sustain such a physical level by connecting the output through a transmission gate to an input pin. For a certain state of the output, one level of an input may be fed through to the output to generate an output voltage level.
In the preferred embodiment of the present invention, a chip select signal {overscore (CS)} is used to define a low level logic signal. An control logic selectively switches a high level logic signal voltage (e.g., V+ supply voltage) or the low level logic signal voltage ({overscore (CS)}) to produce an output digital logic signal.
In a further embodiment of the present invention, separate logic level signals IN
H
and IN
L
may be selectively switched by a control logic to generate an output logic level signal independent of supply voltages V+ and V−.


REFERENCES:
patent: 4174496 (1979-11-01), McFall et al.
patent: 4746899 (1988-05-01), Swanson et al.
patent: 5719573 (1998-02-01), Leung et al.
patent: 5907299 (1999-05-01), Green et al.
patent: 6147631 (2000-11-01), Maulik et al.
“Crystal CS5510/11/12/13 16 and 20-Bit, 8-Pin &Dgr;&Sgr; ADC”, Cirrus Logic, Inc., Sep. 1999.*
“Linear Technology LTC2400 24-Bit &mgr;Power &Dgr;&Sgr; ADC in SO-8”, Linear Technology Corporation, 1998.

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