Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-04-12
2001-10-23
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S530000, C257S536000, C257S538000, C257S543000
Reexamination Certificate
active
06307248
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of defining an anti-fuse cell window in the fabrication of integrated circuits.
(2) Description of the Prior Art
In the fabrication of anti-fuse cells for programmable gate arrays, the current process uses a thin silicon nitride film as a mask in defining the anti-fuse cell window. Because of poor center to edge etching uniformity, silicon nitride residues are often left.
FIG. 1
illustrates a partially completed integrated circuit device. On a semiconductor substrate, a layer of silicon nitride
15
has been deposited over a layer of silicon oxide
14
. In the cell area A, a window
19
is etched, using the silicon nitride layer
15
as a mask. The window is then filled with an insulating layer
26
and polysilicon layer
28
. However, in the active area B, because of the poor etching uniformity, silicon nitride residues
17
are left.
U.S. Pat. No. 4,796,074 to Roesner and U.S. Pat. No. 5,322,812 to Dixit et al show anti-fuse methods and resulting structures.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating an anti-fuse cell for programmable gate array.
A further object of the invention is to provide a method of fabricating an anti-fuse cell for programmable gate array without nitride residues.
Yet another object is to provide a method of fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window.
In accordance with the objects of this invention a method for fabricating an anti-fuse cell using an undoped polysilicon film as a mask in defining the anti-fuse window is achieved. A layer of silicon oxide is provided over the surface of a semiconductor substrate. A first undoped polysilicon layer is deposited overlying the silicon oxide layer. The first undoped polysilicon layer is covered with a photoresist layer patterned to form a mask. The first undoped polysilicon layer and a portion of the silicon oxide layer are etched away where they are not covered by the mask to form a cell opening. The mask and the remaining silicon oxide within the cell opening are removed. An insulating layer is deposited over the surface of the first undoped polysilicon layer and within the cell opening. A second polysilicon layer is deposited overlying the insulating layer and doped. The second polysilicon layer is patterned to form an anti-fuse cell. Gate electrodes and source and drain regions are formed completing the fabrication of the integrated circuit device.
Also in accordance with the objects of this invention, an anti-fuse cell device is described. A first undoped polysilicon layer overlies a silicon oxide layer on the surface of a semiconductor substrate. An insulating layer overlies the first undoped polysilicon layer and contacts the semiconductor substrate at the bottom of a cell opening through the first undoped polysilicon and the silicon oxide layers. A patterned second polysilicon layer overlies the insulating layer within the cell opening to form the anti-fuse cell.
REFERENCES:
patent: 4796074 (1989-01-01), Roesner
patent: 4899205 (1990-02-01), Hamdy et al.
patent: 5070384 (1991-12-01), McCollum et al.
patent: 5242851 (1993-09-01), Choi
patent: 5322812 (1994-06-01), Dixit et al.
patent: 5493147 (1996-02-01), Holzworth et al.
patent: 5508220 (1996-04-01), Eltoukhy et al.
patent: 5514900 (1996-05-01), Iranmanesh
patent: 5619063 (1997-04-01), Chen et al.
patent: 5661071 (1997-08-01), Chor
Chan Lap
Lee Bob
Tan Poh Suan
Wei Che-Chia
Chartered Semiconductor Manufacturing Company
Johnson Chauncey
Meier Stephen D.
Pike Rosemary L. S.
Saile George O.
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