Defining instruction extensions in a standard programming...

Details Defining instruction extensions in a standard programming... Defining instruction extensions in a standard programming...

2008-05-13

2008-05-13

Dam, Tuan (Department: 2192)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C717S146000, C717S150000, C717S159000

Reexamination Certificate

active

10630542

ABSTRACT:
A method is provided for modifying a program written in a standard programming language so that when the program is compiled both an executable file is produced and an instruction is programmed into a programmable logic device of a processor system. The method includes identifying a critical code segment of a program, rewriting the critical code segment as a function, revising the program, and compiling the program. Revising the program includes designating the function as code to be compiled by an extension compiler and replacing the critical code segment of the program with a statement that calls the function. Compiling the program includes compiling the code with an extension compiler to produce a header file and the instruction for the programmable logic device. Compiling the program also includes using a standard compiler to compile the remainder of the program together with the header file to generate the executable file.

REFERENCES:
patent: 4635261 (1987-01-01), Anderson et al.
patent: 4766569 (1988-08-01), Turner et al.
patent: 4893311 (1990-01-01), Hunter et al.
patent: 5055997 (1991-10-01), Sluijter et al.
patent: 5247689 (1993-09-01), Ewert
patent: 5258668 (1993-11-01), Cliff et al.
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5274581 (1993-12-01), Cliff et al.
patent: 5274782 (1993-12-01), Chalasani et al.
patent: 5293489 (1994-03-01), Furui et al.
patent: 5299317 (1994-03-01), Chen et al.
patent: 5343406 (1994-08-01), Freeman et al.
patent: 5357152 (1994-10-01), Jennings, III
patent: 5361373 (1994-11-01), Gilson
patent: 5414377 (1995-05-01), Freidin
patent: 5426378 (1995-06-01), Ong
patent: 5436574 (1995-07-01), Veenstra
patent: 5471628 (1995-11-01), Phillips et al.
patent: 5488612 (1996-01-01), Heybruck
patent: 5517627 (1996-05-01), Petersen
patent: 5535406 (1996-07-01), Kolchinsky
patent: 5619665 (1997-04-01), Emma
patent: 5636224 (1997-06-01), Voith et al.
patent: 5652875 (1997-07-01), Taylor
patent: 5682493 (1997-10-01), Yung et al.
patent: 5684980 (1997-11-01), Casselman
patent: 5696956 (1997-12-01), Razdan et al.
patent: 5726584 (1998-03-01), Freidin
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5784636 (1998-07-01), Rupp
patent: 5819064 (1998-10-01), Razdan et al.
patent: 5822588 (1998-10-01), Sterling et al.
patent: 5847578 (1998-12-01), Noakes et al.
patent: 5850564 (1998-12-01), Ting et al.
patent: 5920202 (1999-07-01), Young et al.
patent: 5926036 (1999-07-01), Cliff et al.
patent: 5956518 (1999-09-01), DeHon et al.
patent: 5963050 (1999-10-01), Young et al.
patent: 5977793 (1999-11-01), Reddy et al.
patent: 5982195 (1999-11-01), Cliff et al.
patent: 5986465 (1999-11-01), Mendel
patent: 5999734 (1999-12-01), Willis et al.
patent: 6092174 (2000-07-01), Roussakov
patent: 6167502 (2000-12-01), Pechanek et al.
patent: 6219628 (2001-04-01), Kodosky et al.
patent: 6237079 (2001-05-01), Stoney
patent: 6292388 (2001-09-01), Camarota
patent: 6343337 (2002-01-01), Dubey et al.
patent: 6353841 (2002-03-01), Marshall et al.
patent: 6374403 (2002-04-01), Darte et al.
patent: 6415424 (2002-07-01), Arimilli et al.
patent: 6418045 (2002-07-01), Camarota
patent: 6426648 (2002-07-01), Rupp
patent: 6557092 (2003-04-01), Callen
patent: 6622233 (2003-09-01), Gilson
patent: 6633181 (2003-10-01), Rupp
patent: 6698015 (2004-02-01), Moberg et al.
patent: 6721884 (2004-04-01), De Oliveira Kastrup Pereira et al.
patent: 6732354 (2004-05-01), Ebeling et al.
patent: 6744274 (2004-06-01), Arnold et al.
patent: 6795900 (2004-09-01), Miller et al.
patent: 6799236 (2004-09-01), Dice et al.
patent: 6817013 (2004-11-01), Tabata et al.
patent: 6831690 (2004-12-01), John et al.
patent: 6857110 (2005-02-01), Rupp et al.
patent: 6874110 (2005-03-01), Camarota
patent: 6883084 (2005-04-01), Donohoe
patent: 6954845 (2005-10-01), Arnold et al.
patent: 6968544 (2005-11-01), Schneider
patent: 6996709 (2006-02-01), Arnold et al.
patent: 7000211 (2006-02-01), Arnold
patent: 7062520 (2006-06-01), Rupp
patent: 7086047 (2006-08-01), Edwards et al.
patent: 7178062 (2007-02-01), Dice
patent: 2001/0049816 (2001-12-01), Rupp
patent: 2003/0046513 (2003-03-01), Furuta et al.
patent: 2003/0097546 (2003-05-01), Taylor
patent: 2003/0108119 (2003-06-01), Mohebbi et al.
patent: 2003/0196058 (2003-10-01), Ramagopal et al.
patent: 2004/0019765 (2004-01-01), Klein, Jr.
patent: 2004/0186872 (2004-09-01), Rupp
patent: 2005/0027970 (2005-02-01), Arnold et al.
patent: 2005/0166038 (2005-07-01), Wang et al.
patent: 2005/0268271 (2005-12-01), Gutberlet et al.
patent: 0 507 507 (1992-07-01), None
patent: 0 668 659 (1995-08-01), None
patent: 1 443 417 (2004-08-01), None
patent: 478252 (2002-03-01), None
patent: 480818 (2002-03-01), None
patent: 509798 (2002-11-01), None
Beeck et al., “Crisp: A Template for Reconfigurable Instruction Set Processors,” FPL 2001, LNCS 2147, pp. 296-305, Springer-Verlag Berlin Heidelberg, 2001.
Bechade, R.A. et al., “Programmable Arithmetic/Logic Circuits,” IBM Technical Disclosure Bulletin, U.S. IBM Corp., New York, vol. 3, No. 11, Apr. 1981, pp. 4870-4873, XP-000713711.
U.S. Appl. No. 10/404,706, Scott D. Johnson, Extension Adapter, filed Mar. 31, 2003.
U.S. Appl. No. 10/686,882, Kenneth Williams, Instruction Set for Efficient Bit Stream and Byte Stream I/O, filed Oct. 15, 2003.
U.S. Appl. No. 10/750,714, Ricardo Gonzalez, Systems and Methods for Software Extensible Multi-Processing, filed Dec. 31, 2003.
U.S. Appl. No. 10/815,453, Ricardo Gonzalez, Configuring a Multi-Processor System, filed Mar. 31, 2004.
U.S. Appl. No. 11/021,247, Ricardo Gonzalez, Systems and Methods for Selecting Input/Output Configuration in an Integrated Circuit, filed Dec. 21, 2004.
U.S. Appl. No. 11/129,146, Ricardo Gonzalez, Long Instruction Word Processing with Instruction Extensions, filed May 12, 2005.
U.S. Appl. No. 11/099,280, Jeffrey M. Arnold, Video Processing System with Reconfigurable Instructions, filed Apr. 4, 2005.
U.S. Appl. No. 11/204,555, Jeffrey M. Arnold, Programmable Logic Configuration for Instruction Extensions, filed Aug. 15, 2005.
Borkar et al., “iWarp: An Integrated Solution to High-Speed Parallel Computing, ” 1988, IEEE CH2617-9/88/0000/03300.
Barat, Francisco and Rudy Lauwereins, “Reconfigurable Instruction Set Processors: A Survey,” 2000, IEEE 0-7695-0668-2/00.
Dehon, Andre, “Transit Note #118 Notes on Coupling Processors with Reconfigurable Logic,” M.I.T. Transit Project, Last Updated March 21, 1995.
Tanenbaum, Andrews S., “Modern Operating Systems,” 2001, 2nd edition, Prentice Hall, New Jersey, p. 31.
Hennessy, John L. and David A. Patterson, “Computer Organization and Design: The Hardware/Software Interface,” 1998, 2nd edition, Morgan Kaufmann Publishers, Inc., San Francisco, CA, p. 345.
Lee, K.C., “A Virtual Bus Architecture for Dynamic Parallel Processing,” Feb. 1993, IEEE Transaction on Parallel and Undistributed Systems, vol. 4, No. 2, pp. 121-130.
Goldblatt, Kim, “The Low-Cost, Efficient Serial Configuration of Spartan FPGAs,” Nov. 13, 1998, XAPP098 (Version 1.0), XILINX.
Scott, Steven L. and Gregory M. Thorson, “The Cray T3E Network: Adaptive Routing in a High Performance 3D Torus,” Aug. 15-16, 1996, HOT Interconnects IV, Stanford University.
Golestani, S. Jamaloddin, “A Sto-and-Go Queuing Framework for Congestion Management,” 1990,Proc. of the ACM Symposium on Communications Architectures & Protocols, ACM Press, New York, NY, pp. 8-18.
Dally, William J. and Charles L. Seitz, “Deadlock Free Message Routing In Multiprocessor Interconnection Networks,” May 10, 1985, Computer Science Department, California Institute of Technology.
Garlan, David and Mary Shaw, “An Introduction to Software Architecture,” Jan. 1994, CMU-CS-94-166, School of Computer Science, Carnegie Mellon University, Pittsburgh, PA.
Intel and Hewlett-Packard, “IA-64 Application Instruction Set Architecture Guide,” Revision 1.0, 1999, pp. C-1 through C.
Hwang, Kai, &#

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