Deficit round-robin scheduling in a high-speed switching...

Details Deficit round-robin scheduling in a high-speed switching... Deficit round-robin scheduling in a high-speed switching...

2008-03-25

2008-03-25

Pham, Chi (Department: 2616)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S229000

Reexamination Certificate

active

10359838

ABSTRACT:
A system for scheduling in a high-speed switching environment includes multiple output queues, multiple counters that each correspond to one of the output queues, and an output port. The output port can read packets from the output queues in a series of rounds. In each of the rounds, the output port can access at least one of the output queues, increment the counter corresponding to the output queue by a first amount, determine whether the counter corresponding to the output queue is at or above a particular level, and, if the counter is at or above the particular level, read one or more packets from the output queue that each have a length and decrement the counter by a second amount corresponding to the one or more lengths of the one or more read packets.

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Cyriel Minkenberg and Ton Engbersen, “A Combined Input and Output Queued Packet-Switched System Based on PRIZMA Switch-on-a-Chip Technology,” IEEE Communications Magazine, pp. 70-77, Dec. 2000.
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M. Shreedhar and George Varghese, “Efficient Fair Queuing using Deficit Round Robin,” pp. 1-21, Oct. 16, 1995.

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