Deferred queuing in a buffered switch

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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Details

C370S416000, C370S395700

Reexamination Certificate

active

10020968

ABSTRACT:
A method and apparatus for temporarily deferring transmission of packets/frames to a destination port in a buffered switch is disclosed. When a request for transmission of at least one packet/frame to the destination port is received, it is determined whether the destination port is available to receive the at least one packet/frame. The transmission of the at least one packet/frame is deferred when the destination port is not available to receive the at least one packet/frame. The packet/frame identifier and memory location for each deferred packet/frame is stored in a deferred queue and the process then repeats for the next packet/frame. Periodically, the apparatus attempts to transmit the packets/frames in the deferred queue to their respective destination ports.

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Gregory L. Frazier & Yuval Tamir, The Design and Implementation of a Multi-Queue Buffer for VLSI Communication Switches, 1989 IEEE.
Kohei Shiomoto, Masayuki Murata, Yuji Oie & Mideo Miyahara, Performance Evaluation of Cell Bypass Queuing Discipline for Buffered Banyan Type ATM Switches, 1990 IEEE.

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