Deferred parity checking of control signals across a bidirection

Details Deferred parity checking of control signals across a bidirection Deferred parity checking of control signals across a bidirection

1987-05-18

1989-04-18

Smith, Jerry

Excavating

371 22, G06F 1110

Patent

active

048233471

ABSTRACT:
Control signal reliability across an I/O limited, high-speed data transmission interface is assured by time-sequenced transmission of control signals and parity signals. Two sets of control signals are transferred in opposing directions across the data transmission interface in a first data transfer period, during which their joint parity is determined and latched on each side of the interface, and the result of one latched joint parity determination is transmitted across the interface. During the following data transfer period, the transmitted parity is compared with the other joint parity determination, the results of the comparison being used to detect transmission errors in the control signals.

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patent: 4556958 (1985-12-01), Ugon
patent: 4737956 (1988-04-01), Zombolas

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