Deferred comparison multiplier checker

Details Deferred comparison multiplier checker Deferred comparison multiplier checker

1989-07-11

1991-05-14

Malzahn, David H.

Boots, shoes, and leggings

G06F 1114

Patent

active

050162080

ABSTRACT:
In a data processing system, a multiplication operation is immediately followed by a redundant multiplication operation, using the same, albeit altered, operands, to check the initial result. The initial result is immediately available for use, but the check is not performed until some time later. The original operands are altered for the redundant multiplication operation by shifting one operand 1 bit, and swapping them before multiplication.

REFERENCES:
patent: 3660646 (1972-05-01), Mirero et al.
patent: 3846626 (1974-11-01), Yoshida
patent: 4314350 (1982-02-01), Toy
Progress Report #2 on the EDVAC Jun. 30, 1946, pp. 1-4-6 and 1-4-7.
Anello et al., "Error Checking by Pseudoduplication", IBM Tech. Disclosure Bulletin, vol. 14, No. 1, Jun. 1971, pp. 16-17.
"Concurrent Error Detection in Multiply and Divide Arrays", Janak H. Patel and Leona Y. Fung, IEEE Transactions on Computers, vol. C-32, No. 4, Apr., 1983 (pp. 417-422).

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