Defect tolerant set associative cache

Details Defect tolerant set associative cache Defect tolerant set associative cache

1989-06-23

1991-12-03

Jablon, Clark A.

Excavating

371 102, 365200, G06F 1120

Patent

active

050705024

ABSTRACT:
It is desirable to bypass the defects within a cache memory so that a high percentage of the cache is usable; otherwise the entire chip containing the cache memory must be scrapped. Since VLSI chips with a small number of defects form a large proportion of the scrapped yield, rendering chips with a small number of defects usable greatly increases the production yield and reduces the cost of each chip. Therefore, a cache memory is provided wherein each memory location includes a bit which is set in response to a detected hardware defect. Preferably, each memory location in the cache is tested by error detecting software, which sets the defect bit in any memory location containing a defect. The defect bit is tested every time data is retrieved from each memory location, and a set defect bit prohibits further use of a defective memory location.

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