Defect tolerant memory

Details Defect tolerant memory Defect tolerant memory

1980-12-04

1983-04-12

Atkinson, Charles E.

Excavating

364900, 365200, G06F 1120, G11C 2900

Patent

active

043800661

ABSTRACT:
The invention is a defect tolerant memory for a computer system. The defect tolerant memory has a main memory, a redundant memory and a mask memory. The redundant memory receives and stores data redundant to that addressed to defective cells in the main memory. The redundant memory has multiple memory levels and uses a randomness technique to store redundant data for all chips of the main memory. The mask memory stores the location of each defect of main memory and indicates when a defective word is addressed in main memory. The mask memory is made up of multiple bit mask memories each cooperating with one of the redundant memory levels. Each bit-mask memory has multiple sub-memory units which use a randomness technique to store the addresses of defects in main memory.

REFERENCES:
patent: 3350690 (1967-10-01), Rice
patent: 3422402 (1969-01-01), Sakalay
patent: 3633175 (1972-01-01), Harper
patent: 4051354 (1977-09-01), Choate
patent: 4051461 (1977-09-01), Hashimoto et al.
patent: 4310901 (1982-01-01), Harding et al.

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