Defect screening using delta VDD

Details Defect screening using delta VDD Defect screening using delta VDD

2001-06-29

2002-11-05

Sherry, Michael (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB, C702S117000

Reexamination Certificate

active

06476631

ABSTRACT:

FIELD
This invention relates to the field of integrated circuit testing. More particularly, this invention relates to detecting defects within functional blocks of integrated circuits.
BACKGROUND
A number of defects can affect the operation of integrated circuits. Of these, delay faults and resistive defects are two of the most difficult defects to detect during quality assurance testing. That these two defects are also among the highest contributors to reliability failures and customer returns compounds the problems associated with delay faults and resistive defects.
Current methods of testing for these types of defects include functional testing of each functional block to a single low supply voltage specification value and a single high supply voltage specification value. In other words, the functional blocks are tested for proper operation at a predetermined low supply voltage value, and are also tested for proper operation at a predetermined high supply voltage value. However, these methods do not allow for comparison of supply voltage values between functional blocks. Also, by not finding the specific supply voltage limits for a given functional block, it is difficult to identify statistical outliers using present methods.
What is needed, therefore, is an improved testing method for defects such as delay faults and resistive defects.
SUMMARY
The above and other needs are met by a method for testing a series of functional blocks within an integrated circuit. Each of the functional blocks in the series is tested to determine a minimum parameter value associated with each of the functional blocks, and each of the functional blocks in the series to tested to determine a maximum parameter value associated with each of the functional blocks.
A minimum parameter delta value is calculated for each of the functional blocks in the series. The minimum parameter delta value is the minimum parameter value associated with a given one of the functional blocks subtracted from the minimum parameter value for a functional block immediately following the given one of the functional blocks in the series.
A maximum parameter delta value is also calculated for each of the functional blocks in the series. The maximum parameter delta value is the maximum parameter value associated with the given one of the functional blocks subtracted from the maximum parameter value for the functional block immediately following the given one of the functional blocks in the series.
The minimum parameter delta value for a given functional block is compared to a minimum parameter delta value tolerance limit. Likewise, the maximum parameter delta value is compared to a maximum parameter delta value tolerance limit. The integrated circuit is selectively binned based at least in part on whether the minimum parameter delta value for any of the functional blocks violates the minimum parameter delta value tolerance limit. Similarly, the integrated circuit is binned based at least in part on whether the maximum parameter delta value for any of the functional blocks violates the maximum parameter delta value tolerance limit.
By testing each functional block to failure, both for a minimum parameter value and a maximum parameter value, the integrated circuit can be screened for statistical outliers that might normally pass a functional test at a predetermined low specification limit and a predetermined high specification limit, but which might fail in actual use over a period of time.
In one embodiment of the testing method, the minimum parameter delta value tolerance limit and the maximum parameter delta value tolerance limit are absolute limits, or in other words, predetermined specification limits. However, in a preferred embodiment, the minimum parameter delta value tolerance limit and the maximum parameter delta value tolerance limit are statistically calculated limits, based at least in part on the data collected from the functional blocks over time. Thus, as the intrinsic minimum or maximum parameter values increase or decrease due to process variation or other variables, there will not tend to be excessive yield loss, because the present method compares delta values rather than an absolute value.
In a preferred embodiment of the method, the steps of selectively binning the integrated circuit include rejecting the integrated circuit as defective. Also preferably, the parameter being tested is a supply voltage, also called the VDD level. The steps of testing each of the functional blocks in the series are performed at a predetermined elevated or lowered temperature in one preferred embodiment of the method. It is also appreciated that the steps of testing each of the functional blocks in the series are, in another preferred embodiment, performed at a functional speed greater than a rated functional speed for the integrated circuit.
In another embodiment, all of the steps of the testing method are performed on a single testing device. In an alternate embodiment, the steps of testing each of the functional blocks in the series are performed on a testing device (on tester) and the steps of calculating, comparing, and selectively binning are performed on a separate analyzing device (off tester). The steps of selectively binning the integrated circuit may include burning in and retesting the integrated circuit.
According to another aspect of the invention an apparatus is described for accomplishing the method as described above. In yet another aspect of the invention a program is described for controlling a programmable apparatus to accomplish the method as described above.


REFERENCES:
patent: 5386189 (1995-01-01), Nishimura et al.
patent: 5804960 (1998-09-01), El Ayat et al.
patent: 5864566 (1999-01-01), Sanada
patent: 6104985 (2000-08-01), Sowards

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