Optics: measuring and testing – Inspection of flaws or impurities – Surface condition
Reexamination Certificate
1999-12-09
2002-08-20
Pham, Hoa Q. (Department: 2877)
Optics: measuring and testing
Inspection of flaws or impurities
Surface condition
C356S237500, C250S559400, C250S205000
Reexamination Certificate
active
06437862
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a defect inspection apparatus for inspecting an object, such as a wafer and a chip, for defects.
2. Description of the Background Art
Defects include extraneous material adhering to a surface of an object, and a pattern defect of an object. A semiconductor device will be taken as an example of the objects to be inspected in the description below.
FIG. 19
is a schematic block diagram of a background art defect inspection apparatus. As illustrated in
FIG. 19
, the background art defect inspection apparatus comprises an X-Y stage
101
for placing thereon a wafer
100
to be inspected, an objective lens
102
, a Xe lamp
103
, a TV camera
104
, an A/D converter
105
, an image memory
106
, and a defect judgement device
107
.
FIG. 20
is a partially enlarged top plan view of the wafer
100
. As illustrated in
FIG. 20
, the wafer
100
has a plurality of chips
110
arranged in a matrix.
Description is given on a method of inspecting a circuit pattern
111
b
fabricated into a chip
110
b
for defects, using the defect inspection apparatus shown in FIG.
19
. First, the X-Y stage
101
is moved to position the wafer
100
so that the Xe lamp
103
illuminates the circuit pattern
111
b
. Next, the Xe lamp
103
directs light onto the circuit pattern
111
b
. The light reflected from the circuit pattern
111
b
passes through the objective lens
102
and reaches the TV camera
104
. The TV camera
104
detects the reflected light as an image. The A/D converter
105
converts the detected image into a digital signal to input the digital signal as image data DB to the defect judgement device
107
.
The image memory
106
has previously inputted image data DA concerning a circuit pattern
111
a
fabricated into a chip
110
a
. The defect judgement device
107
receives the image data DA from the image memory
106
, and then subtracts the image data DA from the image data DB to determine a difference therebetween.
FIG. 21
shows the image data DA, the image data DB, and the difference data DB−DA. The image data DA, DB and the difference data DB−DA are shown in plan view in the upper part of
FIG. 21
, and a digital value representing brightness as measured along the line L is illustrated in the lower part of FIG.
21
. If the circuit pattern
111
b
has a defect, the defect appears as defect data
112
in the image data DB. When the brightness of the defect data
112
is not less than a predetermined threshold value X
1
as a result of the subtraction of the image data DA from the image data DB, the defect judgement device
107
judges that the circuit pattern
111
b
has a defect in a position corresponding to the defect data
112
.
However, such a background art defect inspection apparatus has presented problems to be described below.
First Problem
As described hereinabove, the background art defect inspection apparatus compares the value of the difference data DB−DA provided by subtracting the image data DA from the image data DB with the predetermined threshold value X
1
to judge the presence or absence of a defect. A wafer subjected to the CMP process often has different thicknesses depending on locations in the wafer surface. In such a case, the difference in thickness causes a difference in reflected light intensity. Thus, the value of the difference data DB−DA is not zero but is detected as noises in a nondefective location (FIG.
22
). It is therefore difficult to determine whether the difference data DB−DA having a value not less than the threshold value X
1
results from a defect or noises. The use of a higher threshold value X
2
so as not to detect noises makes it impossible to detect the defect data. Additionally, in combination with the decrease in pattern resolution when detected due to performance limitations of optical systems with recent size reduction of semiconductor devices, the background art defect inspection apparatus presents the problem of low defect detection accuracy.
Second Problem
Some defects in a chip are fatal to semiconductor devices, but some are not. This depends on the positions in which the defects occur in a chip. However, the background art defect inspection apparatus detects all defects in the chip independently of the positions in which the defects occur. Hence, the background art defect inspection apparatus is not capable of judging whether or not the detected defects affect a yield in practice. This results in delayed measures against process failures and the production of dust which give rise to defects, accordingly leading to the increase in manufacturing costs.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a defect inspection apparatus comprises: a light illuminator for directing light onto a surface of an object to be inspected; a data generator for generating illumination light control data for rendering the intensity of light reflected from the surface uniform throughout the surface, based on a distribution of reflectance of the surface for the light; a light intensity controller for controlling the intensity of the light directed from the light illuminator onto the surface, based on the illumination light control data; and an inspector receiving the light reflected from the surface or scattered by the surface and for inspecting the surface for a defect.
Preferably, according to a second aspect of the present invention, in the defect inspection apparatus of the first aspect, the light intensity controller includes: a liquid crystal filter having a filter surface disposed in an optical path between the light illuminator and the surface; and a filter controller for controlling transmittance of the filter surface for the light, based on the illumination light control data.
Preferably, according to a third aspect of the present invention, in the defect inspection apparatus of the second aspect, the liquid crystal filter is a filter capable of non-uniformly controlling the transmittance in the filter surface.
Preferably, according to a fourth aspect of the present invention, in the defect inspection apparatus of any one of the first to third aspects, the object is a wafer having a surface coated with a film.
Preferably, according to a fifth aspect of the present invention, in the defect inspection apparatus of any one of the first to third aspects, the object is a wafer having a plurality of chips arranged in a matrix; the data generator generates the illumination light control data based on the reflectance for each of the chips or for each of dice; and the light intensity controller controls the intensity of the light for each of the chips or for each of the dice.
Preferably, according to a sixth aspect of the present invention, in the defect inspection apparatus of any one of the first to third aspects, the object is a wafer having a plurality of chips arranged in a matrix; the data generator receives classification data concerning the plurality of chips classified into a first group of chips and a second group of chips in accordance with a predicted distribution of the reflectance of a wafer surface of the wafer; the data generator determines a first reflectance of at least one representative first chip included in the first group as the reflectance of the first group of chips, and determines a second reflectance of at least one representative second chip included in the second group as the reflectance of the second group of chips; and the light intensity controller controls the intensity of the light for each of the first and second groups.
Preferably, according to a seventh aspect of the present invention, in the defect inspection apparatus of any one of the first to third aspects, the object is a wafer having a plurality of chips arranged in a matrix; the data generator receives classification data concerning the plurality of chips classified into a first group of chips expected to be more susceptible to defects and a second group of chips expected to be less susceptible to defe
Ikeno Masahiko
Miyazaki Yoko
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Pham Hoa Q.
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