Defect insertion testability mode for IDDQ testing methods

Details Defect insertion testability mode for IDDQ testing methods Defect insertion testability mode for IDDQ testing methods

1996-09-26

1999-02-09

Oda, Christine K.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324537, 3241581, G01R 3126

Patent

active

058699775

ABSTRACT:
A Defect Insertion Testability Mode for IDDQ Testing to detect defects in a semiconductor device and for accuracy correction during testing. In one embodiment of the present invention a screen condition and a known defect current are selected for the device under test (DUT). The DUT is screened without a known defect current being inserted and then is screened again with a known defect current inserted. The results of screening the DUT with and without the known defect current are then compared and the screen condition is adjusted based upon this comparison in order to increase the accuracy of the IDDQ test.

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Robert C.Aitken, A Comparison of Defect Models For Fault Location With IDDQ Measurements, IEEE, Reprint from Proceedings International Test Conference 1992, pp. 335-344. (no month).
Charles F. Hawkins and Jerry M. Soden, Electrical Characteristics and Testing Considerations For gate Oxide Shorts In CMOS ICs, IEEE, Reprint from Proceedings International Test Conference 1995, pp. 313-324. (no month).

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