Deep via construction for a semiconductor device

Details Deep via construction for a semiconductor device Deep via construction for a semiconductor device

2006-09-19

2010-12-21

Chambliss, Alonzo (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

Mesa structure

C257S774000, C257SE23011, C257SE23145, C257SE23145, C257SE23145, C174S262000, C174S264000, C438S637000, C438S640000

Reexamination Certificate

active

07855438

ABSTRACT:
An integrated circuit semiconductor device includes a substrate, a deep via within the substrate which is provided with a dielectric cladding in contact with the substrate, metal fill located within the deep via and defining an upper surface, interconnect wiring, and a dielectric layer located above the deep via and a void between the upper surface of the metal fill and the dielectric layer. The interconnect wiring layer contacts the metal fill laterally.

REFERENCES:
patent: 6093966 (2000-07-01), Venkatraman et al.
patent: 7091618 (2006-08-01), Yoshizawa et al.
patent: 2005/0009329 (2005-01-01), Tanida et al.
patent: 2006/0043598 (2006-03-01), Kirby et al.
patent: 2007/0096329 (2007-05-01), Suzuki et al.

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