Deep UV anti-reflection coating etch

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

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Details

438725, 438724, 438736, 216 47, H01L 21302

Patent

active

059104538

ABSTRACT:
An etching process for DUV photolithography is provided for etching a layer of anti-reflection coating (ARC) comprising spin-on organic ARC material which is formed beneath a layer of photoresist. After patterning the layer of photoresist, the layer of ARC is etched by employing a mixture of oxygen plasma, nitrogen plasma, and at least one inert gas. Anisotropic etching of the layer of ARC is provided with the process of the present invention. In comparison with prior art etching processes for etching a layer of ARC, the process of the present invention provides a favorable etch rate with improved selectivity over the etching of the layer of photoresist. The layer of ARC is etched without causing lateral erosion of the layer of photoresist. Faceting of the top edges of the corners of the layer of photoresist is also minimized. The profile of the layer of photoresist is essentially maintained thereby enabling for critical dimension fidelity. The process of the present invention is residue-free, and provides favorable selectivity for etching the layer of ARC over most underlying materials conventionally used in integrated circuit structures. The layer of ARC can also be etched by employing a mixture of nitrogen plasma and inert gas. Employing a mixture of nitrogen plasma and inert gas, without oxygen plasma, provides a reduced etch rate.

REFERENCES:
patent: 4624909 (1986-11-01), Saotome et al.
patent: 4751170 (1988-06-01), Mimura et al.
patent: 4968582 (1990-11-01), Tranjan et al.
"DUV Lithography For 0.35-.mu.m CMOS Processing"; Van Driessche et. al.; 1995; Microelectronics Eng., 27(1-4), pp. 243-245.

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