Deep trench self-alignment process for an active area of a...

Details Deep trench self-alignment process for an active area of a... Deep trench self-alignment process for an active area of a...

2006-06-06

2006-06-06

Goudreau, George A. (Department: 1763)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S243000, C438S697000, C438S700000, C438S714000, C438S717000, C438S719000, C438S734000

Reexamination Certificate

active

07056832

ABSTRACT:
A deep trench self-alignment process for an active area of a partial vertical cell. A semiconductor substrate with two deep trenches is provided. A deep trench capacitor is formed in each deep trench, and an isolating layer is formed thereon. Each trench is filled with a mask layer. A photoresist layer is formed on the semiconductor substrate between the deep trenches, and the photoresist layer partially covers the mask layer. The semiconductor substrate is etched lower than the isolating layer using the photoresist layer and the mask layer as masks. The photoresist layer and the mask layer are removed, such that the pillar semiconductor substrate between the deep trenches functions as an active area.

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