Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2006-02-07
2006-02-07
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S510000
Reexamination Certificate
active
06995449
ABSTRACT:
According to an exemplary method for removing a hard mask in a deep trench isolation process, a hard mask is formed over the substrate, where the substrate includes at least one field oxide region. Thereafter, a trench is formed in the substrate, where the trench has a first sidewall and a second sidewall. According to this exemplary embodiment, the hard mask is removed after forming the trench. The hard mask may be removed by, for example, etching the hard mask in an anisotropic dry etch process, where the anisotropic dry etch process is selective to nitride and silicon. Next, an oxide liner is deposited by a CVD process on the first and second sidewalls of the trench and over the substrate after the hard mask has been removed.
REFERENCES:
patent: 4835115 (1989-05-01), Eklund
patent: 4871685 (1989-10-01), Taka et al.
patent: 5106777 (1992-04-01), Rodder
patent: 6406972 (2002-06-01), Norstrom et al.
Kalburge Amol
Yin Kevin Q.
Cao Phat X.
Doan Theresa T.
Farjami & Farjami LLP
Newport Fab LLC
LandOfFree
Deep trench isolation region with reduced-size cavities in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Deep trench isolation region with reduced-size cavities in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Deep trench isolation region with reduced-size cavities in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3699471