Deep submicron MOS transistors with a self-aligned gate electrod

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257314, 257315, 257316, 257344, 257413, 257414, H01L 2976

Patent

active

061555371

ABSTRACT:
A MOS transistor with a pair of lightly doped drain (LDD) sub-regions in the substrate and whose gate electrode is self-aligned with a non-doped gate oxide layer overlying the channel region between the two LDD sub-regions. The MOS transistor is characterized as having the following structure: (a) a substrate having a source region and a drain region; (b) a gate oxide layer on the substrate which overlays the source and drain regions, the gate oxide layer containing a central portion and two side portions, the central portion being a non-doped, and the side portions being lightly doped with a dopant; (c) a gate electrode formed on the gate oxide layer, the gate electrode having a base self-aligned with the central non-doped portion of the gate oxide layer; (d) a pair of sidewall spacers formed on sidewalls of the gate electrode, each of the sidewall spacers having a base self-aligned with a respective lightly doped side portion of the gate oxide layer; and (e) a pair of non-contiguous lightly dopes drain (LDD) sub-regions formed in the substrate. The LDD sub-regions respectively underlie the lightly doped side portions of the gate oxide layer and are formed by thermal diffusion of dopants therefrom, the LDD sub-regions are also respectively adjacent to the source and drain regions and are facing each other to define a channel region therebetween.

REFERENCES:
patent: 5654568 (1997-08-01), Nakao
patent: 5675161 (1997-10-01), Thomas
patent: 5736765 (1998-04-01), Oh et al.
patent: 5932909 (1999-08-01), Kato et al.
patent: 5939749 (1999-08-01), Taketa et al.

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