Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2001-05-18
2003-02-11
Lebentritt, Michael S. (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S514000, C257S516000, C257S522000
Reexamination Certificate
active
06518641
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor device manufacturing, and in particular to a method of fabricating a deep slit isolation region that includes a void intentionally formed within a lower portion of the isolation region. The present invention also relates to the deep slit isolation region formed by the inventive method as well as semiconductor structures that include the inventive deep slit isolation region.
BACKGROUND OF THE INVENTION
As integrated circuit (IC) device technology has advanced and IC dimensions have become smaller and smaller, it has become increasingly common within advanced ICs to employ trench isolation methods such as shallow trench isolation (STI) methods and recessed oxide isolation (ROI) methods to form trench isolation regions that are nominally coplanar with adjoining active semiconductor device regions of semiconductor substrates. However, recent advances in semiconductor technologies have required deeper isolation regions driven by vertical transistors in dynamic random access memory (DRAM) devices. Conventional methods have only allowed the shallow trench isolation to reach depths of about 2500 Å because it is difficult to etch a deep trench region with a resist mask and it is also difficult to fill the etched deep trench region with a dielectric fill material such as an oxide. There is therefore a need for developing an improved method for forming deep trench isolation regions.
This is especially the case wherein vertical transistor devices having longer channel lengths are desired; longer channel lengths typically result in a semiconductor structure having lower off-state leakage as compared with vertical transistor devices having short channel lengths. Lower off-state leakage thus drives the need for deeper isolation regions between the devices. It is well known in the art that a deep trench region may be etched into a semiconductor substrate using an oxide hardmask on top of a pad nitride layer. Recent advancements in the field of fabricating trench isolation regions include the methods described in U.S. Pat. No. 6,140,207 to Lee and U.S. Pat. No. 6,150,212 to Divakaruni, et al. Specifically, the '207 patent is directed to a method of forming isolation regions within a semiconductor device that includes the steps of forming a masking layer on a semiconductor substrate, said masking layer defining field areas and active areas; forming a first trench and a second trench in the field areas of the semiconductor substrate, wherein the first trench has a width that is greater than that of the second trench; and forming an insulating layer in the first and second trench, wherein the insulating layer formed in the second trench has a void beneath a surface of the semiconductor substrate.
Although the '207 patent discloses a means for providing an isolation region in a semiconductor substrate that has a void formed therein, the '207 patent does not provide a means for allowing electrical continuity of the adjacent P-well, nor does it provide a means for avoiding charge loss due to floating well effects. Moreover, the '207 patent does not provide a trench isolation region which results in lower support sheet resistivity.
The '212 patent mentioned above relates to a method for forming an isolation trench region in a semiconductor substrate which includes the steps of: providing a trench region in a semiconductor substrate; forming a spacer material at least along sidewalls of the trench region; etching the trench region at the bottom surface so as to extend the trench region beyond the bottom surface thereby forming a crevice region beneath the trench region; and heating the spacer material such that the spacer material flows from the sidewalls of the trench region into the crevice region. Note that the '212 patent teaches away from intentionally forming a void in the trench region.
In view of the above, there is a need for providing a method of forming isolation regions which allows for electrical continuity of the adjoining array P-well, avoids charge loss due to floating well effects, results in lower support sheet resistivity and reduces noise for low-voltage applications.
SUMMARY OF THE INVENTION
One object of the present invention is to provide sub-minimum width/high aspect ratio isolation for contemporary applications using minimum lithographic image sizes.
A further object of the present invention is to provide isolation regions that enable extreme scaling (below a feature size, F of about 90 nm).
A yet further object of the present invention is to provide isolation regions that have improved latch-up immunity.
Another object of the present invention is to provide isolation regions that have a low-dielectric constant associated therewith which provides for reduced coupling at small groundrules.
These and other objects and advantages are achieved in the present invention by providing isolation regions in which the isolation regions include at least one trench region having sidewalls that extend to a bottom surface and a slit region formed beneath the final trench region, said slit region being narrower than the overlying trench regions and having a void formed therein.
One aspect of the present invention relates to a method of forming the inventive deep slit isolation region in a surface of a semiconductor substrate which includes the steps of:
(a) forming a first trench region in a surface of a substrate, said first trench region having sidewalls extending to a bottom surface;
(b) forming first spacers on said sidewalls of said first trench region;
(c) forming a slit region through said bottom surface of said first trench region, said slit region having a narrower width than said first trench region; and
(d) filling said first trench region and said slit region with at least one dielectric material so as to form a void within said slit region.
Following the above filling step, the inventive method may also include a planarizing step. In one embodiment of the present invention, a plurality of trenches, in addition to the first trench region, is formed in the substrate prior to forming the slit region. In such an embodiment, wherein a plurality of trenches is formed in the substrate, each successive trench region has a narrower width than the preceding trench region and the final trench region has an adjoining slit region that is formed through the bottom surface thereof.
Another aspect of the present invention relates to an isolation region (hereinafter referred to as a “deep slit isolation region”) which is prepared from the inventive method. Specifically, the inventive deep slit isolation region comprises:
a first trench region having sidewalls extending to a first shoulder region; and
a slit region extending from said first shoulder region, wherein said first trench region and said slit region are filled with at least one dielectric material, and said slit region contains a void therein.
In one embodiment of the present invention, a plurality of trench regions, in addition to the first trench region, is present above the slit region. In such an embodiment, each successive trench region has a width that is narrower than the preceding trench region, and the final trench region would include the slit region formed form the shoulder region thereof.
Another aspect of the present invention relates to a memory cell such as a DRAM which includes at least one of the inventive deep slit isolation regions therein. Specifically, the memory cell of the present invention comprises:
at least a pair of active device regions which include a plurality of spaced apart vertical dynamic random access memory cells, wherein said pair of active device regions are isolated from each other by an adjoining deep slit isolation region, said deep slit isolation region comprising a first trench region having sidewalls extending to a first shoulder region; and a slit region extending from said first shoulder region, wherein said first trench region and said slit region are filled with at least one dielectri
Divakaruni Ramachandra
Faltermeier Johnathan E.
Mandelman Jack A.
Tonti William R.
Lebentritt Michael S.
Li Todd M.C.
Scully Scott Murphy & Presser
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