Deep isolation trenches

Details Deep isolation trenches Deep isolation trenches

2002-12-30

2004-11-23

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S697000, C257SE21546

Reexamination Certificate

active

06821865

ABSTRACT:

BACKGROUND OF THE INVENTION
Deep isolation trenches filled with a dielectric material, such as oxide, are used to isolate devices of an integrated circuit. Deep isolation trenches are particularly useful for isolating memory cells employing trench capacitors with vertical transistors. Such types of memory cells are described in, for example. U. Gruening et al, “A Novel Trench DRAM Cell with a Vertical Access Transistor and Buried Strap (VERI BEST) for 4 Gb/16 Gb”, International Electron Device Meeting (IEDM '99) Technical Digest, pp. 25-28, 1999, when is herein incorporated by reference for all purposes. A plurality of memory cells are interconnected by wordlines and bitlines to form a memory array. The memory array forms, for example, a memory IC, such as dynamic random access memory (DRAM) IC.
The devices of an IC can be arranged in different configurations or layouts. Typically, the layout includes areas with densely and non-densely packed device regions. For example, a memory IC comprises densely packed memory cells (transistors and storage nodes) in the array region and loosely packed support circuitry in the non-array region. The size of devices can also vary widely, resulting in deep isolation trenches and active areas located in between them having different widths.
FIG. 1
shows a cross-sectional view of a portion of a partially processed memory IC. As shown, the substrate includes array and non-array regions
105
and
106
. Typically, narrower and more densely packed deep isolation trenches
130
are located in the array region to separate memory cells and wider and less densely packed isolation trenches
120
are located in the non-array region. The isolation trenches are
The aspect ratio (i.e., depth/width) of the deep trenches in the array region is about 3:1 or higher. The depth of the trench is typically about 300 to 700 nm below the silicon level. To effectively fill trenches with such high aspect ratio, high density plasma (HDP) chemical vigor deposition (CVD) techniques are used. This is because HDP-CVD techniques have a higher vertical fill rate relative to the sidewall growth rate, which increases the gapfill capability compared to conventional conformal CVD techniques such as low pressure CVP (LPCVD) or sub-atmosphere CVD (SA-CVD), HDP-CVD techniques also produce a denser oxide than other conventional CVD techniques, which is not easily affected by subsequent etch processes.
A unique surface topography, in which the oxide protrudes angularly from the trenches, is produced by HDP-CVP. Substantially sloping edges are formed as the oxide layer coats the surface of the substrate. The excess material on the surface of the substrate is subsequently removed by chemical mechanical polishing (CMP). Due to the depth of the deep trenches, a thick oxide deposition is required to completely fill the trenches. The thick oxide deposition results in an equally thick dielectric layer over the surface of the substrate. This thick oxide deposition makes planarization by CMP very difficult, and often results in dishing 127 in wide openings and poor uniformity in the removal of excess oxide from the surface of the substrate. Poor uniformity can lead to variations in device characteristics and shorting problems between, for example, wordlines to wordlines with bitlines.
Another problem associated with HDP oxide is that voids can be formed in the deep isolation trenches. Although the vertical rate of deposition is much higher than the horizontal component (about 3:1 to 10:1), the high aspect ratio of the isolation trenches may result in the opening at the top being closed before completely filling the trenches. This results in voids being formed in the deep isolation trenches. Voids near the surface of the isolation trenches next to the active areas are extremely critical, causing a leakage of currents or even shorting of woldlines or wordlines with bitlines, rendering the isolation trenches ineffective.
From the above discussion, there is desire to improve the fabrication of deep isolation trenches, which avoids dishing, poor uniformity and voids.
SUMMARY OF INVENTION
The present invention relates to the fabrication of ICS. More particularly, the invention relates to a method of forming deep isolation trenches in the fabrication of ICs. A substrate is prepared with deep isolation trenches. In accordance with the invention, the isolation trenches are partially filled with a first dielectric material. In one embodiment, an etch mask layer is used to remove excess first dielectric material on the surface of the substrate. The isolation trenches are then completely filled with a second dielectric material. Excess second dielectric material is removed from the surface of the substrate. By filling the deep isolation trenches in multiple fill steps, various advantages such as better planarity and uniformity are obtained.


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