Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2000-07-03
2001-11-27
Bowers, Charles (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S506000, C257S374000, C257S392000, C438S224000
Reexamination Certificate
active
06323532
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to controlling the amount of gate wrap-around within metal oxide semiconductor field effect transistors by adjusting the depth of divots within the shallow trench isolation adjacent the gates.
2. Description of the Related Art
It is well recognized that divots in shallow trench isolation (STI) regions adjacent transistor wells, which are a consequence of removing the sacrificial oxide layers in surface-channel N-type metal oxide semiconductor field effect transistors (NFET's), are responsible for causing the gate conductor to “wrap-around” the silicon corners in NFET's which results in poor threshold voltage (Vt) controllability of the NFETs. Such divots
12
,
13
are shown adjacent a buried-channel PFET device in FIG.
1
. Because of this poor threshold voltage controllability, the doping concentration within the P-well beneath the gate conductor is increased in order to meet the target off-current (e.g., the drain-source current where the field effect transistor i off-“Ioff”).
However, a problem exists with this conventional solution of increasing the doping concentration because a drastically increased array junction leakage has been observed with increased P-well surface concentration (e.g., a surface concentration greater than 5×10
17
cm
−3
). Because of this array NFET problem arising from the STI divot, there has been great interest in minimizing divot depth.
The invention minimizes divot depth for NFET devices and at the same time avoids causing problems with other devices manufactured on the same wafer, such as buried-channel PFET devices.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method of forming, on a semiconductor substrate, first gate conductors which wrap around N-wells of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells of buried-channel N-type metal oxide semiconductor field effect transistors. The inventive method comprises forming insulators adjacent each of the N-wells and the P-wells, protecting the P-wells with patterned mask, forming first divots in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators adjacent P-wells, wherein the first divots have a greater depth than the second divots.
The process of forming the first divots comprises etching the insulators from portions of sides of the N-wells and the process of forming the second divots maintains the insulators on sides of the P-wells.
The method also includes forming gate conductors over the N-wells and the P-wells, such that respective ones of the gate conductors cover a top surface of the P-wells and others of the gate conductors cover a top surface and side surfaces of the N-wells. Additionally, the N-wells have a depleted region within a surface P-layer and the first divots are formed to have a depth greater than a depth of the depleted region.
In another embodiment the method includes forming insulators adjacent each of the N-wells and the P-wells, protecting the N-wells with patterned mask and leaving the P-wells exposed, implanting a first impurity in the P-wells, removing the first patterned mask, protecting the P-wells with second patterned mask and leaving the N-wells exposed, implanting a second and third impurity in the N-wells, forming first divots in areas of the insulators adjacent the N-wells, removing the second patterned mask, and forming second divots in areas of the insulators adjacent the P-wells, wherein the first divots have a greater depth than the second divots.
The invention also comprises a semiconductor structure having buried-channel P-type metal oxide semiconductor field effect transistors having N-wells and first gate conductors covering tops and portions of sides of the N-wells, and surface-channel N-type metal oxide semiconductor field effect transistors having P-wells and second gate conductors covering tops of the P-wells.
The inventive structure also includes first shallow trench isolation (STI) regions adjacent the N-wells and having first divots, and second shallow trench isolation regions (STI) adjacent the P-wells and having second divots, wherein the first divots have a depth greater than that of the second divots. Also, the N-wells include a depleted P-type region adjacent the first gate conductors and the first gate conductors cover the sides of the N-wells to a depth greater than a depth of the depleted P-type region. Further, the N-wells and the P-wells are positioned on a single substrate.
The invention controls the amount of gate wrap-around within field effect transistors by adjusting the depth of divots within the shallow trench isolation regions adjacent the gates. The invention is a single process which forms a deep divot in buried-channel PFET devices and a shallow divot depth in surface-channel NFET devices on the same substrate and, by doing so, provides reduced sub-threshold swing, off-current, parasitic edge conduction, hot-electron degradation and sensitivity to the presence of charge adjacent to the device sidewall.
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Joachim Hans-Oliver
Mandelman Jack A.
Rengarajah Rajesh
Bowers Charles
International Business Machines - Corporation
Kielin Erik
McGinn & Gibb PLLC
Petraske, Esq. Eric W.
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