Dedicated service processor with inter-channel communication fea

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364DIG2, 3649425, 3649423, 364933, 3649332, 3649337, G06F 1300

Patent

active

051290782

ABSTRACT:
A system comprises a service processor and a plurality of operating units dependent on the service processor. The service processor responds to service requests from the operating units and services the operating units one at a time. A scheduler is responsible for assigning priority to the operating units and determining the order in which the service requests are handled. A register contains a value indicative of the operating unit currently being serviced and is under control of the scheduler. According to one aspect of the present invention the register is also under control of the service processor itself. Another register, under control of the service processor, is coupled to the scheduler to generate service requests thereto independent of the operating units. A memory addressable by the service processor stores data. The service processor is capable of generating addresses for the memory derived from the contents of the register indicative of the operating unit currently being serviced.

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patent: 4268902 (1981-05-01), Bergland et al.
patent: 4325119 (1982-04-01), Grandmaison et al.
patent: 4494194 (1985-01-01), Harris et al.
patent: 4630232 (1986-12-01), Loskorn et al.
patent: 4837677 (1989-06-01), Burrus, Jr. et al.

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