Multiplex communications – Pathfinding or routing – Combined circuit switching and packet switching
Reexamination Certificate
2007-07-03
2007-07-03
Pham, Chi (Department: 2616)
Multiplex communications
Pathfinding or routing
Combined circuit switching and packet switching
C370S392000, C370S352000, C370S401000, C370S389000, C709S236000, C709S230000
Reexamination Certificate
active
10102931
ABSTRACT:
A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit may include a single execution section and the L3 generation unit may include multiple parallel execution sections. When both the L2 and L3 generation units complete their operations on a particular packet, a build component combines the generated L2 and L3 information to form a complete packet header.
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Libby Jeffrey G.
Lim Raymond M.
Harrity & Snyder LLP
Jain Raj K.
Juniper Networks, Inc.
Pham Chi
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