Dedicated ALU architecture for 10-bit Reed-Solomon error correct

Details Dedicated ALU architecture for 10-bit Reed-Solomon error correct Dedicated ALU architecture for 10-bit Reed-Solomon error correct

1995-06-14

1998-07-07

Elmore, Reba I.

Excavating

371 375, 371 401, H03M 1300

Patent

active

057780099

ABSTRACT:
A system architecture for implementing a 10-bit Reed-Solomon code for detecting and correcting data errors in a single code word to protect a data block containing up to 1023 10-bit data symbols, i.e., the equivalent of up to 1278 8-bit symbols, including error check redundancy, maximizes the use of all allocated error correction overhead for an entire block of data, regardless of the particular error pattern characteristics encountered in a given system application. The architecture is particularly well suited for digital data processing and/or storage systems encountering non-bursty, (i.e., substantially random), error patterns, such is characteristic of data storage and retrieval systems employing semiconductor based memory stores. 5-bit extension field operations, (i.e., over a Galois field GF(2.sup.5)), generated by using the irreducible polynomial, P.sub.32 (X)=X.sup.5 +X.sup.2 +1, over GF(2), are utilized to perform certain, requisite arithmetic functions over the Galois field GF(2.sup.10) with a hardware-minimized error correction architecture.

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