Decoupling capacitor configuration for integrated circuit chip

Details Decoupling capacitor configuration for integrated circuit chip Decoupling capacitor configuration for integrated circuit chip

1999-02-13

2001-02-20

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S532000, C257S533000

Reexamination Certificate

active

06191479

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to power distribution system design, and in particular to managing disturbances otherwise caused by time varying current demands in an integrated circuit.
2. Description of the Related Art
As high performance integrated circuits demand larger currents at higher frequencies with lower power supply voltages, power system design becomes increasingly challenging. For example, next generation microprocessors will demand peak currents in excess of 100 A and reach operating frequencies of 1 GHz with power supply voltages below 2 V. At such current levels, surge currents and associated excitations of power distribution system resonances can result in significant power supply voltage excursions. Accordingly, reductions in the AC impedance of a power distribution system, particularly inductive components thereof, are desired.
A variety of techniques are available to improve the AC impedance characteristics of a power distribution system. One such technique involves the appropriate placement of decoupling structures/devices, e.g., capacitors, throughout the power distribution system. Others include chip layout with respect to power distribution, use of low inductance packaging technologies such as Controlled Collapse Chip Connection (C4) and Ball Grid Array (BGA) for delivery of supply voltages (V
DD
and V
SS
), BGA package design and layers, card layout and use of discrete capacitance placed thereon, connector selection and V
DD
/V
SS
allocations, regulator choice, and lastly the motherboard layout.
In a typical computer system configuration, inductances are associated with the vias, traces, connectors, etc. of an integrated circuit carrier (or “package”), of a daughterboard card, and of a motherboard. At low frequencies (i.e., below approximately 100 KHz), impedance of the power supply loop circuit can be made arbitrarily low through the utilization of feedback voltage sensing at the power supply. At very high frequencies, the impedance of the power supply loop circuit can be lowered with the use of on-die capacitance to approximately (1/&ohgr;C) where &ohgr; is the angular frequency (such that &ohgr;=2&pgr;f) and C is the capacitance associated with the power supply loop circuit including the on-die capacitance. Unfortunately, in the mid-frequencies (e.g., from approximately 1 MHz to 100 MHz), the AC impedance of the power supply loop circuit is likely to exhibit resonances.
While the impedance at both high- and mid-frequencies can be managed through the use of decoupling capacitors placed strategically in the power supply loop circuit, two significant challenges exist. First, spatial limitations of an integrated circuit chip can limit the amount of capacitance provided on-die. Typically, only the portions of the die that are free from device structures will be available for fabrication of on-die capacitors. High-frequency, high-current integrated circuits such as advanced microprocessors may require hundreds of nF of on-die capacitance. Even worse, larger capacitances, e.g., &mgr;f, will be required to manage mid-frequency resonances. Using conventional gate oxide dielectric techniques and typical gate oxide thicknesses, capacitance on the order of 10 nF per mm
2
can be achieved. Therefore, achieving hundreds to thousands of nF of on-die capacitance requires significant die footprint (e.g., tens to hundreds of mm
2
). Such die footprint can adversely affect die size and yield.
Many off-chip decoupling capacitor configurations have been developed. For example, U.S. Pat. No. 4,754,366 to Hernandez discloses flat decoupling capacitors adapted for mounting directly under a Pin Grid Array (PGA) package, directly under a surface-mounted Plastic Leaded Chip Carrier (PLCC), and over a surface-mounted leadless chip carrier. U.S. Pat. No. 4,636,918 to Jodoin and U.S. Pat. No. 5,034,850 to Hernandez et al. disclose other discrete off-chip decoupling capacitor configurations. Unfortunately, the inductive impedance of intervening portions of the power supply loop circuit (e.g., of chip and package -level interconnect features such as vias, traces, bonding pads, wires and wire bonds, Tape Automated Bonded (TAB) traces and bonds, solder bumps including Controlled Collapse Chip Connection (C4) bumps, etc.) typically limits the efficacy of off-chip decoupling capacitors.
In part for this reason, decoupling capacitors have also been provided integral with an integrated circuit package. For example, U.S. Pat. No. 5,258,575 to Beppu et al. discloses a plurality of small discrete decoupling capacitors connected to integral power and ground planes of an integrated circuit package. U.S. Pat. No. 5,475,565 to Bhattacharyya et al. discloses a decoupling capacitor configuration wherein the decoupling capacitor is mounted to and electrically connected to a lid of an electronic package. U.S. Pat. No. 5,049,979 to Hashemi et al. discloses a close attach capacitor attached above the top of a TAB chip wherein short bonded wires or TAB leads interconnect the capacitor electrodes with power and ground pads on the chip.
Unfortunately, even in such configurations, the series inductance from the switching circuits of the integrated circuit to the decoupling capacitance limits the efficacy of the decoupling capacitance. Accordingly, decoupling capacitor configurations are desired which allow placement of large decoupling capacitance on-die with extremely low intervening inductance.
SUMMARY
A decoupling capacitor structure formed integral with an integrated circuit chip and over top of circuitry defined thereon advantageously provides decoupling capacitance in close electrical proximity to switching circuits of the integrated circuit chip without substantially affecting die footprint. In contrast with on-die gate oxide capacitor configurations, a decoupling capacitor structure formed toward the back end of processing, typically after interconnect metal, allows large area capacitor structures without substantial impact on area available for devices and circuitry. Inductance associated with the intervening portion of a power supply loop circuit between switching circuits of the integrated circuit chip and the decoupling capacitor structure can be extremely low in configurations in accordance with the present invention. In some configurations, connection points, e.g., bonding pads and/or solder bumps for conveying power supply voltages, are defined over top of the decoupling capacitor structure.
In some embodiments in accordance with the present invention, an integrated circuit chip includes circuitry defined thereon including device structures and conductive traces and a thin-film capacitor formed over the circuitry and electrically coupled thereto. In some configurations, the integrated circuit chip also includes conductive vias formed at least partially through the thin-film capacitor from respective of the conductive traces. Each of a first group of the conductive vias is electrically connected to a first conductive plate of the thin-film capacitor and perforates, without connecting to, a second conductive plate of the thin-film capacitor. Each of a second group of the conductive vias is electrically connected to the second conductive plate. In some configurations, the integrated circuit chip also includes plural connection points defined thereon, wherein at least a portion of the first group of conductive vias extend to respective connection points, and wherein at least a portion of the second group of conductive vias perforate, without connecting to, the first conductive plate and extend to respective connection points. In some configurations, a third group of conductive vias is formed through said thin-film capacitor from respective of the connection points to respective signal voltage conveying conductive traces. The third conductive vias perforate, without connecting to, conductive plates of the thin-film capacitor. In some configurations, power supply voltages are introduced to the circuitry of the integrated circuit chip via t

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