Decoupled scan path interface

Details Decoupled scan path interface Decoupled scan path interface

1993-12-22

1995-01-10

Cosimano, Edward R.

Excavating

371 225, G06F 1128

Patent

active

053814207

ABSTRACT:
An interface to internal scan paths within an IC for synchronizing a test clock and a system clock without adversely affecting their operation. The test clock provides input test data (TDI) to the interface and receives output test data (TDO) from the interface at the test clock rate. The system clock drives the test data through the scan path at the system clock rate. The two clocks are "decoupled" in that they run independently, being synchronized by the interface for clocking the test data into, through and out of the scan path. In effect, the interface decouples the internal scan paths driven by the system clock from the test logic driven by the test clock. This feature enables the IC to be tested "at speed" and provides for synchronization between the test clock and system clock over a wide range of test clock frequencies.

REFERENCES:
patent: 5254942 (1993-10-01), D'Souza et al.
patent: 5329471 (1994-07-01), Swoboda et al.
"IEEE Standard Boundary Scan 1149.1" by John Andrews, presented at Electro International Conference 1991, New York, pp. 522-527 (Apr. 16-18, 1991).
"JTAG Works to Standardize Chip, Board and System Self-Test" by Warren Andrews, Technology Updates, Computer Design, pp. 28-31 (Jul. 1, 1989).
"Scan-Design Methods Increase Testability of Standard Cells" by Mark A. Buchanan, Computer Design, pp. 79-82 and 84 (Mar. 1, 1986).
"An Intuitive Look at Metastability" by Byron I. Moyer, Electronic Engineering Times, p. 37 (Mar. 9, 1992).

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