Decompression bit processing with a general purpose...

Details Decompression bit processing with a general purpose... Decompression bit processing with a general purpose...

2003-01-31

2004-06-29

Treat, William M. (Department: 2183)

Electrical computers and digital processing systems: processing

Byte-word rearranging, bit-field insertion or extraction,...

C712S221000, C712S223000, C712S224000

Reexamination Certificate

active

06757820

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to processors and, more particularly to instructions for use with processors.
2. Related Art
In order to support speech, audio,
3
D-graphics and video compression and decompression, processors must be able to support a variety of operations such as bit extraction, digital signal processing (DSP) and image display. As the demand for faster rendering of high resolution images rises, hardware acceleration of these operations becomes more and more important. Prior art processors, however, have focused on DSP and signal display operations while providing only limited support for bit extraction operations.
On the other hand, when dealing with encoded multimedia data such as H.261, H.265, MPEG-1, MPEG-2 or MPEG-4 data, as much as 50% of the processing time may be spent on bit extraction operations. As a result, there is a need for a general purpose processor that allows for fast processing of bit extraction operations.
SUMMARY OF THE INVENTION
The present invention provides a method and apparatus for performing fast bit extraction operations in a general purpose processor. The fast bit extraction operations are accomplished by executing a first instruction for extracting an arbitrary number of bits of a sequence of bits stored in two or more source registers of the processor starting at an arbitrary offset and the storing the extracted bits in a destination register. Both the source and the destination registers are specified by the instruction. In addition, a second instruction is provided for counting the number of leading zeros in a sequence of bits stored in two or more source registers of the processor and then storing a binary value representing the number of leading zeros in a destination register. Again the source and the destination registers are specified by the second instruction.
Both the first and the second instructions are pipelined to obtain an effective throughput of one instruction every cycle. As a result, bit extraction operations are performed very efficiently by the processor, thereby reducing the overall processing time required to compress and decompress multimedia data. The bit extraction instruction can also be used as an instruction to obtain unaligned data.


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U.S. patent application Ser. No. 09/442,874, filed Nov. 18, 1999, entitled “Decompression Bit Processing with a General Purpose Alignment Tool,” naming inventors Subramania Sudharsanan, Jeffrey Meng Wah Chan and Marc Tremblay, 29 pp.
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