Decoding system capable of reducing sector select area...

Details Decoding system capable of reducing sector select area... Decoding system capable of reducing sector select area...

2007-11-05

2009-11-03

Le, Vu A (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185020

Reexamination Certificate

active

07613042

ABSTRACT:
Methods and apparatus are disclosed for erasing memory cells in a virtual ground memory core, wherein a row decoder apparatus employs a protective voltage to wordlines of a sector of cells while concurrently providing an erase voltage to selected wordlines of the same physical sector. Decoder circuitry and methods are disclosed for selecting a memory cell sector to be erased and adjacent sectors to be protected, which may be used in single bit and dual bit memory devices, and which enable column decoder circuitry to reduce the number of sector select circuits.

REFERENCES:
patent: 5719808 (1998-02-01), Harari et al.
patent: 5949713 (1999-09-01), Bedarida et al.
patent: 5982665 (1999-11-01), Xing et al.
patent: 6898662 (2005-05-01), Gorobets
patent: 7049652 (2006-05-01), Mokhlesi et al.
patent: 2004/0141439 (2004-07-01), Suzuki et al.
patent: 2005/0157553 (2005-07-01), Perroni et al.
patent: 2008/0130359 (2008-06-01), Maayan et al.

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