Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1993-01-06
1994-01-11
Gossage, Glenn
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
365 51, 365 63, 307449, 307463, G11C 800, G11C 502, G11C 506
Patent
active
052788024
ABSTRACT:
A word or row line (38a, 38b) associated with at least one row of memory cells in an integrated circuit memory array (10) having a plurality of word lines is driven by a drive/boot generator signal (RLXH) by first generating this drive signal using a drive signal generator (20) that is formed in a peripheral area (14) of the chip (10). The drive signal (RLXH) is transmitted to each of a plurality of predecoders (40) that are formed within a memory cell array area (12) of the chip (10). At least one of the predecoders (40) is actuated to transmit the drive signal (RLXH) onto a selected one of a plurality of predecoder output lines (RDD0-RDD3) in response to predetermined addressing or row factor signals (RF0-RF19). The drive signal (RLXH) is transmitted on a selected predecoder output line (44) to each of a plurality of decoders (36) formed within the array area (12). At least one of the decoders (36) actuated to transmit the drive signal (RLXH) from the addressed predecoder output line (RDD0-RDD3) to at least a selected one of a plurality of word lines (38a, 38b) in response to predetermined ones of the addressing or "row factor" signals signals (RF0-RF19). The selected word lines (38a, 38b) are then driven and booted using the decoded drive/boot signal (RLXH).
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Childers Jimmie D.
Kersh, III David V.
Bassuk Larry J.
Castro Rose K.
Gossage Glenn
Neerings Ronald O.
Texas Instruments Incorporated
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