Decoding control with address transition detection in page...

Details Decoding control with address transition detection in page... Decoding control with address transition detection in page...

2007-02-27

2009-08-18

Luu, Pho M. (Department: 2824)

Static information storage and retrieval

Addressing

Byte or page addressing

C365S230050, C365S230060, C365S230010, C365S230080, C365S235000, C365S185290, C365S185330, C365S185110, C365S185120, C711S119000, C711S149000

Reexamination Certificate

active

07577059

ABSTRACT:
Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of each address of the multi-page erase operation. In the event the addresses relate to pages in different blocks, then previously latched page addresses are reset. This avoids the incorrect circuit operation that will result should a multi-page erase operation include multiple pages in different blocks.

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