Decoding circuit for use in semiconductor read only memory

Static information storage and retrieval – Addressing

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36523006, G11C 800

Patent

active

055770037

ABSTRACT:
A decoding circuit for use in a semiconductor read only memory includes a predecoding unit receiving a first address signal group of a given address, for generating a plurality of word selection driving signals, and a plurality of decoder blocks each receiving a second address portion of the same address different from the first address signal group. Each of the decoder blocks includes a selecting unit receiving the second address signal group for outputting an active first word selection control signal when the decoder block is designated by the second address signal group, and a pair of word selecting units receiving the first word selection control signal and a third address signal group of the same address different from the first and second address signal groups, for generating a pair of second complementary word selection control signals and another pair of third complementary word selection control signals. Each decoder block also includes a plurality of decoding units each including a series-circuit constituted of first, second, third and fourth series-connected transistors, having their control electrode connected to receive the second and third complementary word selection control signals, respectively. Opposite ends of the series-circuit are connected to receive a corresponding one of the word selection driving signals. A connection node between the first and second transistors generates a first word selecting signal, and a connection node between the third and fourth transistors generates a second word selecting signal. Only one of the word selecting signal is activated at a time.

REFERENCES:
patent: 5159215 (1992-10-01), Murotani
patent: 5297084 (1994-03-01), Ban
patent: 5440518 (1995-08-01), Hazani

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