Decoding circuit for runlength codes

Details Decoding circuit for runlength codes Decoding circuit for runlength codes

1995-10-11

1997-11-18

Gaffin, Jeffrey A.

Coded data generation or conversion

Digital code to digital code converters

To or from run length limited codes

3582611, H04N 141

Patent

active

056892543

ABSTRACT:
After all the data words stored in a first scan transform RAM are initialized to "0"s, only signed level data words are overwritten, based on zero runlength data words, on "0"s at the positions designated by zigzag scan addresses in the first scan transform RAM. Thus, while only non-zero components out of 8.times.8 components forming one block are written in the first scan transform RAM, a block stored in a second scan transform RAM is read and initialized. Further, while only non-zero components of the next block are written in the second scan transform RAM, the block stored in the first scan transform RAM is read and initialized. This achieves, in real time, highly efficient runlength decoding responsive to a picture element clock signal of high frequency.

REFERENCES:
patent: 5369045 (1994-11-01), Choi et al.
ISO/IEC Committee Draft 13818-2, Information Technology-Generic Coding of of Moving Pictures and Associated Audio, Nov., 1993, pp. 57-64.

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