Decoding circuit for memory device

Details Decoding circuit for memory device Decoding circuit for memory device

2007-02-27

2007-02-27

Phan, Trong (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189080, C365S233100

Reexamination Certificate

active

10941552

ABSTRACT:
Provided is a decoding circuit for a memory device which is improved in an operation of chip so as to enable the operation to be predictable by making a decoded result corresponding to an undefined code get a specific value. The decoding circuit for a memory device generates address signals by control signals set with a mode, and comprises a first logical circuit for decoding and outputting a result value defined by logically-combining the address signals corresponding to a first group and a second logical circuit for performing a decoding operation to have address signals with a specific value included in the defined result value by logically-combining address signals corresponding to a second group, by dividing the address signals into the first group corresponding to at least one defined result value and the second group corresponding to an undefined result value.

REFERENCES:
patent: 5673233 (1997-09-01), Wright et al.
patent: RE37273 (2001-07-01), Shinozaki
patent: 6337809 (2002-01-01), Kim et al.
patent: 6483579 (2002-11-01), Koshikawa
patent: 6489819 (2002-12-01), Kono et al.

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