Decoding circuit for inhibiting error propagation

Details Decoding circuit for inhibiting error propagation Decoding circuit for inhibiting error propagation

1990-09-28

1993-11-23

Canney, Vincent P.

Excavating

371 377, 371 42, 371 671, G06F 1110

Patent

active

052651053

ABSTRACT:
A decoding circuit receives signals encoded in differential logical conversion, and decodes the received signals into original signals. During the decoding, a predetermined data bit position included in the original signals is detected in the received signal, and also the predetermined data is forcedly set to the bit position of the decoded signal, thereby bit error propagation is suppressed up to the position of the known data.

REFERENCES:
patent: 4530094 (1985-07-01), Sewerinson
patent: 5130993 (1992-07-01), Gutman et al.
Patent Abstracts of Japan, vol. 14, No. 85 (E-08990) Feb. 16, 1990, & JP-A-01 296840 (Fujitsu) Nov. 30, 1989.
Patent Abstracts of Japan, vol. 11, No. 374 (E-562) Dec. 5, 1987, & JP-A-62 141875 (Fujitsu) Jun. 25, 1987.
Patent Abstracts of Japan, vol. 12, No. 174 (E-612) (3021) May 24, 1988, & JP-A-62 281531 (NEC) Dec. 7, 1987.
Patent Abstracts of Japan, vol. 8, No. 185 (E-262) Aug. 24, 1984, & JP-A-59 075741 (Akai) Apr. 28, 1984.
Patent Abstracts of Japan, vol. 11, No. 051 (E-480) Feb. 17, 1987, & JP-1-61 214630 (Canon) Sep. 24, 1986.

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