Decoding circuit for flat panel display

Details Decoding circuit for flat panel display Decoding circuit for flat panel display

2011-06-28

2011-06-28

Williams, Howard (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

With particular solid state devices

C341S144000

Reexamination Certificate

active

07969338

ABSTRACT:
The present invention relates to a decoding circuit for a flat panel display, and more particularly to a decoding circuit for a flat panel display wherein a miniaturization is possible by reducing an area of the circuit. There is provided a decoding circuit comprising: a first decoder for selecting a predetermined number of gradation voltages from a plurality of gradation voltages according to a least significant bit or least significant bits of an image data; a second decoder for selecting one of the selected gradation voltages to be outputted to an output terminal according to a plurality of selection signals; and a third decoder for outputting the plurality of the selection signals according to a most significant bit or most significant bits of the image data, wherein a minimum length of gates of a plurality of MOSFETs included in the first decoder is shorter than that of a plurality of MOSFETS included in the second decoder.

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patent: 5999115 (1999-12-01), Connell et al.
patent: 6075477 (2000-06-01), Kokubun et al.
patent: 6232941 (2001-05-01), Ode et al.
patent: 6608612 (2003-08-01), Kokubun et al.
patent: 7126518 (2006-10-01), Tsuchi
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patent: 2000-156639 (2000-06-01), None
patent: 2001-036407 (2001-02-01), None
patent: 2003-029687 (2003-01-01), None
patent: 2005-017933 (2005-01-01), None
Machine Translation of JP 2001-036407 from http://ipdl.inpit.go.jp on Oct. 20, 2010.

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