Decoding circuit for flash-type analog-to-digital converter

Details Decoding circuit for flash-type analog-to-digital converter Decoding circuit for flash-type analog-to-digital converter

1988-05-19

1989-11-28

Shoop, Jr., William M.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341155, H03M 136

Patent

active

048840750

ABSTRACT:
In a parallel (or "flash") type analog-to-digital converter (ADC), a decoding technique and apparatus. First, the output of every comparator is examined relative to its nearest neighbors. If, for comparator "n", the outputs of "neighboring" comparators "n+1" and "n-1" both are in a different state than the output of comparator "n", the output state of comparator "n" is reversed. That is, each group of three adjacent comparators (n-1, n and n+1) is examined and the output of the "center" comparator is "corrected" by substituting the majority state of the three comparators for the output of the "center" comparator (i.e., comparator "n"). Second, the zeroes-to-ones transition point is found in the thus-corrected outputs. Once the transition point is found, a conventional encoding produces a digital output word. Circuitry is provided for the efficient implementation of the method and for performing the method in an equivalent single step.

REFERENCES:
patent: 4596978 (1986-06-01), Fujita
patent: 4719447 (1988-01-01), Garuts
Peetz et al., "An 8-bit 250 Megasample per Second Analog-to-Digital Converter: Operation without a Sample and Hold", IEEE Journal of Solid-State Circuits, vol. SC-21, 12/86, pp. 997-1002.

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