Coded data generation or conversion – Digital code to digital code converters – To or from interleaved format
Reexamination Certificate
1999-12-06
2002-02-12
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
To or from interleaved format
C714S752000
Reexamination Certificate
active
06346896
ABSTRACT:
BACKGROUND OF THE INVENTION
This application incorporates by reference Taiwanese application Ser. No. 88105564, filed Apr. 8, 1999.
1. Field of the Invention
The invention relates in general to a signal-decoding device and a decoding method, and more particularly to a device and method for deinterleaving data stored on disks.
2. Description of the Related Art
It is sometimes possible that a compact disk (CD) may suffer from physical damage, for example, scratches, during production or use. To prevent logical continuous data from being lost as a result of the physical damage, a data scramble technique is typically employed during the data-write process of CD read-only-memory (CD-ROM) production. In short, each logical continuous data stream is first divided into a plurality of blocks according to a predetermined algorithm. Afterwards, another algorithm is employed to scramble blocks of one logical continuous data stream with blocks of other logical continuous data streams. The resulting scrambled data are then sequentially and continuously written into the physical spaces of the CD-ROM. When, unfortunately, a certain portion of the CD-ROM is damaged, the portion of damaged data belonging to one logical continuous data stream may be recovered by the associated un-damaged data of the respective logical continuous data stream via the algorithm. Therefore, in addition to the raw data, some extra data, including control code, sync code, and protection code are added to the raw data to form the complete data in the CD-ROM.
In order to prevent data damage or loss, when original data are to be stored in disks, the following encoding operations are sequentially performed: C
3
encoding, C
2
encoding, interleaving, and C
1
encoding.
The interleaving operation repartitions frames of C
2
coded data into different frames for C
1
coding. After interleaving, if data is damaged, the damaged data is dispersed among different frames of the decoded data, and thus correction probability is enhanced.
Therefore, when data in a disk is read, the following decoding operations are sequentially performed: C
1
decoding, deinterleaving, C
2
decoding, and C
3
decoding. Deinterleaving is a reverse operation of interleaving.
Referring to
FIG. 1
, which shows a conventional deinterleaving operation. Each frame of C
1
coded data includes 32 bytes, in which there are 4 bytes of parity check. After C
1
coded data is parity-checked by the 4 parity bytes, 28 bytes of parity-checked C
1
coded data are obtained.
As shown, in
FIG. 1
, a first byte (byte
0
) of the parity-checked C
1
coded data is delayed for 27×4=108 cycles and then provided to a C
2
decoder. A cycle represents a transmission unit of a frame. Similarly, a second byte (byte
1
) of the parity-checked C
1
coded data is delayed for 26×4=104 cycles and then provided to the C
2
decoder. Byte
2
of the parity-checked C
1
coded data is delayed for 25×4=100 cycles and then provided to the C
2
decoder. The relation is summarized as follows: byte k is delayed for (27−k)×4 cycles and then provided to the C
2
decoder. Thus, byte 27 of the parity-checked C
1
coded data is delayed for 0×4=0 cycles and then provided to the C
2
decoder
Each byte of the parity-checked C
1
coded data is transmitted to the C
2
decorder in pipeline mode. Between each byte received by the C
2
decoder, there is a 4-frame transmission cycle delay.
That is to say, byte
0
of a first C
2
frame received by the C
2
decoder comes from byte
0
of the first C
1
frame. Byte
1
of the first C
2
frame comes from byte
1
of a fifth C
1
frame. Byte
2
of the first C
2
frame comes from byte
2
of a ninth C
1
frame.
A symbol “D” in
FIG. 1
represents delay registers. Each delay register is used to delay bytes of the C
1
frame for one cycle. That is to say, in
FIG. 1
, there are 108, 104, . . . , 4, 0 delay registers used for delaying bytes
0
,
1
, . . .
27
of the C
1
and C
2
coders.
However, a disadvantage of this conventional scheme is that it uses a large number of delay registers. As shown in
FIG. 1
, it is clear that such a conventional system requires 108+104+ . . . +4+0=1512 delay registers to implement the deinterleaving process. The number of logic gates used for implementing so many delay registers is 44 k in total.
Therefore, according to the conventional system, a deinterleaving device is very complicated because 44 k logic gates are used. Circuit designers must take a great deal of time to design and debug such a system. The total cost for providing this large number of gates and testing the final design is high.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an improved and simplified device and method for deinterleaving data, for example during signal-decoding. By applying the present invention, the hardware cost can be reduced, and the circuit designer can design and debug the circuit more easily.
The invention achieves the above-identified objects by providing a method of deinterleaving bytes of a framed input signal to provide a deinterleaved framed output signal. The method includes: generating a write address A
1
; receiving sequential bytes of the input signal; storing the received bytes as write data according to the write address A
1
; generating a read address A
2
; and producing the output signal as sequential bytes of read data according to the read address A
2
. Generating a write address A
1
includes: setting initial values of input parameters which correspond to characteristics of a current received byte; generating an initial write address based on the initial values of the input parameters; changing the values of ones of the input parameters to correspond to a next received byte; and repeatedly generating the write address A
1
based on the changed values of the input parameters. Storing the received bytes as write data includes sequentially writing each of the received bytes to a respective memory address corresponding to the write address A
1
. Generating a read address A
2
includes: setting initial value of output parameter which corresponds to characteristics of a current byte of read data; generating an initial read address based on the initial value of the output parameter; changing the value of the output parameter after each byte of read data is provided; and repeatedly generating the read address A
2
based on the changed value of the output parameter. Providing the output signal as bytes of read data includes reading sequential bytes of the read data from a memory address corresponding to the read address A
2
. The invention is particularly applicable where the input signal is a parity-checked C
1
-coded signal having a 28-byte frame, and the output signal is a C
2
-coded signal having a 28-byte frame.
Preferably, the input parameters include a first input parameter I
1
, a second input parameter K
1
, and a third input parameter D. The first input parameter I
1
corresponds to a frame identification of a current received byte. The second input parameter K
1
corresponds to a byte identification of the current received byte. The third input parameter D corresponds to a delay identification of the current received byte. Likewise, the output parameters preferably include a output parameter I
2
. The output parameter I
2
corresponds to a frame identification of a current byte of read data. Accordingly, an initial value of the first input parameter I
1
corresponds to the number of frames in the input signal. An initial value of the second input parameter K
1
corresponds to the first byte of the input signal. An initial value of the third input parameter D corresponds to an initial interleave delay between bytes in a frame of the input signal.
Further, changing the values of ones of the input parameters to correspond to a next received byte includes changing the parameters such that K
1
=K
1
+1 and D=D+N if K
1
<B.
The “N” corresponds to a number of clock cycle interl
Chen Shin Yung
Su Wei-Ming
Jeanglaude Jean Bruner
Jeanpierre Peguy
Rabin & Berdo, P.C
Via Technologies Inc.
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