Decoding apparatus

Details Decoding apparatus Decoding apparatus

1995-01-11

1996-10-15

Coles, Sr., Edward L.

Facsimile and static presentation processing

Facsimile

Recording apparatus

358426, 358433, H04N 144

Patent

active

055659918

ABSTRACT:
A decoding circuit in which the data error does not propagate to the next DCT block. In response to a reset signal for a decoding process, a down-counter reads a process number set in a process number setting unit, and counts down the process number according to the entered clock pulses. A comparator compares the count of the down-counter and the non-zero/zero-run mixed data from a lookup table, and releases an A<B flag in case the latter is larger. The A<B flag is supplied to a first OR gate and a NAND gate, and, if it is an H-level, forcedly shifts the non-zero/zero-run flag to the H-level and sends the flag to an up-counter 8 and a second OR gate. At the same time the outputs of the NAND gate and the first OR gate are logically multiplied and sent to an AND gate group, which replaces the zero-run data with non-zero data "0".

REFERENCES:
patent: 4737765 (1988-04-01), Minuhin
patent: 4813056 (1989-03-01), Fedele
patent: 4903269 (1990-02-01), Fedele
patent: 5218622 (1993-06-01), Fazel et al.

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