Decoding and selection circuit for a monolithic memory

Details Decoding and selection circuit for a monolithic memory Decoding and selection circuit for a monolithic memory

1981-06-22

1983-07-19

Popek, Joseph A.

Static information storage and retrieval

Powering

Conservation of power

365230, G11C 700

Patent

active

043947522

ABSTRACT:
A word line selection circuit includes a conventional Schottky diode decoder and a driver transistor which is connected to a word line. A word line is selected when the transistor is conductive and all associated diodes of the decoder are off. The base current of the driver transistor is defined by a control transistor whose conductivity is opposite to that of the driver transistor and which applies the selection current to the base of the driver transistor. A regulating transistor forms a current mirror with the control transistor to regulate the selection current. A compensation circuit associated with the regulating transistor modulates the collector current of the regulating transistor as a function of the driver transistor factor.

REFERENCES:
patent: 4007451 (1977-02-01), Heuber et al.
patent: 4295210 (1981-10-01), Beranger et al.
V. Marcello et al., "Decode Circuit with Up-Level Clamp" vol. 20 No. 11A, Apr. 1978, pp. 4406-4408, IBM Technical Disclosure Bulletin.
J. A. Dorler et al., "Complementary Transistor Switch Memory Cell", vol. 16, No. 12, May 1974, pp. 3931-3932, IBM Technical Disclosure Bulletin.

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