Decoder with reduced synchronization capture time

Details Decoder with reduced synchronization capture time Decoder with reduced synchronization capture time

1988-09-30

1990-04-17

Shoop, Jr., William M.

Coded data generation or conversion

Digital code to digital code converters

With error detection or correction

341 87, 341107, 371 46, H03M 1312

Patent

active

049184466

ABSTRACT:
A decoder is capable of decoding on a maximum likelihood basis coded symbols of requivalently high coding rate which are produced by deleting those code bits which are located at particular positions in a time sequence of convolutional symbols of low coding rate. The decoder includes a serial-to-parallel (SP) converter for converting a serial data sequence from a dummy bit inserter into parallel sequences. The frequency division phase of the SP converter is determined by a second timing signal which the dummy bit inserter produces in synchronism with a dummy bit inserted phase. A code synchronization is established, frequency division phase synchronization is automatically established. This eliminates the need for the repetitive trial for frequency division phase synchronization only and thereby reduces a synchronization capture time.

REFERENCES:
patent: 4747104 (1988-05-01), Piret
patent: 4805174 (1989-02-01), Kubota
patent: 4855742 (1989-08-01), Verboom

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