Decoder unit with clamp transistor preventing excessive voltages

Details Decoder unit with clamp transistor preventing excessive voltages Decoder unit with clamp transistor preventing excessive voltages

1988-04-21

1989-05-23

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307452, 307453, 307463, 307550, H03K 19003

Patent

active

048333484

ABSTRACT:
For elimination of mis-decoding operation, there is disclosed a decoder unit comprising a logic gate having input nodes respectively supplied with data bits of an input signal and carried out a logical operation to decide a logic level at an output node thereof, a precharging transistor responsive to a precharging signal and providing a conduction path between a source of positive voltage and the output node of the logic gate for charging the output node of the logic gate to a positive precharging level, an output circuit responsive to the logic level at the output node of the logic gate for producing an output signal, and a compensating transistor responsive to the voltage level at the output node of the logic gate and operative to provide a conduction path between the output node of the logic gate and the source of positive voltage, so that the compensating transistor allows an excess voltage to be discharged from the output node to the source of positive voltage, thereby preventing the decorder unit from the mis-decoding operation due to the excess voltage level at the output node of the logic gate.

REFERENCES:
patent: 4025908 (1977-05-01), DeRemer et al.
patent: 4087044 (1978-05-01), Hofmann
patent: 4275312 (1981-06-01), Saitou et al.
patent: 4381460 (1983-04-01), Menachem
patent: 4398102 (1983-08-01), Stewart
patent: 4563598 (1986-01-01), Oritani
patent: 4692638 (1987-09-01), Stiegler
patent: 4728827 (1988-03-01), Woo
patent: 4737936 (1988-04-01), Takeuchi

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