Decoder structure for a folded logic array

Details Decoder structure for a folded logic array Decoder structure for a folded logic array

1975-11-06

1977-05-24

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

235152, 307205, 307DIG5, 328 92, H03K 1920, G11C 506

Patent

active

040257991

ABSTRACT:
This specification describes a decoder for use in a programmable logic array (PLA) of the type having opposite ends of input lines of the array connected to outputs of different decoders. Instead of using the outputs of two two-bit decoders to drive four input lines, as was previously done, four one-bit decoders are used to drive the four input lines. This arrangement permits the one-bit decoders with minor modifications to be used to perform four one-bit decodes of four input signals, two two-bit decodes on two sets of two input signals on either side of the array and one two-bit decode on two input signals that are on opposite sides of the array.

REFERENCES:
patent: 3816725 (1974-06-01), Greer
patent: 3829846 (1974-08-01), Berg et al.
patent: 3849638 (1974-11-01), Greer
patent: 3936812 (1976-02-01), Cox et al.
Howley et al., "Programmable Logic Array Decoding Technique"; IBM Tech. Discl. Bull.; vol. 17, No. 10, pp. 2988; Mar. 1975.

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