Decoder of digital-to-analog converter

Details Decoder of digital-to-analog converter Decoder of digital-to-analog converter

2007-09-04

2007-09-04

Jeanglaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C257S258000

Reexamination Certificate

active

11364725

ABSTRACT:
In a decoder of a digital-to-analog converter, the gamma voltage selection is controlled by a reduced number of NMOS and PMOS transistors according to the characteristic of the NMOS and PMOS transistor, such that the layout area of the switch array is reduced. Moreover, a N-type buried diffusion (BDN) layer and a P-type buried diffusion (BDP) layer are adopted to replace the contacts in the layout of conventional decoder, such that the layout can be simplified and the bump pad pitch thereof can be decreased.

REFERENCES:
patent: 6459331 (2002-10-01), Takeuchi et al.
patent: 2001/0052867 (2001-12-01), Ureshino
patent: 2002/0100925 (2002-08-01), Hsiao et al.

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