Decoder lockout defeat circuit

Details Decoder lockout defeat circuit Decoder lockout defeat circuit

1983-10-03

1985-12-10

Buczinski, S. C.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

328155, H04N 7167

Patent

active

045583609

ABSTRACT:
A suppressed sync television decoder includes a phase locked horizontal oscillator for controlling operation of a suppressed sync detector which supplies a circuit for restoring suppressed sync in a television signal. The restored sync is coupled to the phase locked oscillator and to a first four bit counter. A second four bit counter is supplied with the horizontal oscillator signal and inhibits counting in both counters when it counts 16. A reset signal corresponding to the end of the vertical interval initializes both counters. If the number of sync pulses counted by the second counter is less than 16, an error signal is produced. Thirty-two error signals result in generation of a defeat pulse to unlock the oscillator.

REFERENCES:
patent: 4029900 (1977-06-01), Addeo
patent: 4222068 (1980-09-01), Thompson
patent: 4354164 (1982-10-01), Gupta
patent: 4419760 (1983-12-01), Bjornholt
patent: 4489347 (1984-12-01), Tentler

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