Decoder interface

Details Decoder interface Decoder interface

2008-03-18

2008-03-18

Kindred, Alford (Department: 2181)

Electrical computers and digital processing systems: processing

Processing architecture

Microprocessor or multichip or multimodule processor having...

Reexamination Certificate

active

10912897

ABSTRACT:
Method and apparatus for a decoder interface for a processor and a coprocessor is described. An input instruction register stores an input instruction from the processor. Configuration instruction registers store instructions. Comparison/pointer logic coupled to the input instruction register and the configuration instruction registers is configured to compare the input instruction from the processor with the instructions stored in the configuration registers to determine if there is a match, and configured to provide a pointer associated with a configuration instruction register of the configuration instruction registers having a instruction of the instructions matching the input instruction, where the pointer has fewer bits than the input instruction.

REFERENCES:
patent: 4785453 (1988-11-01), Chandran et al.
patent: 4965717 (1990-10-01), Cutts et al.
patent: 5276823 (1994-01-01), Cutts et al.
patent: 5440749 (1995-08-01), Moore et al.
patent: 5784640 (1998-07-01), Asghar et al.
patent: 5809336 (1998-09-01), Moore et al.
patent: 5838165 (1998-11-01), Chatter
patent: 5914616 (1999-06-01), Young et al.
patent: 5987598 (1999-11-01), Levine et al.
patent: 6032247 (2000-02-01), Asghar et al.
patent: 6052773 (2000-04-01), DeHon et al.
patent: 6122747 (2000-09-01), Krening et al.
patent: 6247113 (2001-06-01), Jaggar
patent: 6434689 (2002-08-01), Fleck et al.
patent: 6480952 (2002-11-01), Gorishek et al.
patent: 6519710 (2003-02-01), Saunders et al.
patent: 2003/0062922 (2003-04-01), Douglass et al.
patent: 2004/0044878 (2004-03-01), Evans et al.
patent: 2004/0193852 (2004-09-01), Johnson
patent: 2005/0172105 (2005-08-01), Doering et al.
“Memory Interfacing and Instruction Specification for Reconfigurable Processors”; Jacob et al.; 1999; ACM.
“Garp: A MIPS Processor with a Reconfigurable Coprocessor”; Hauser et al.; 1997; IEEE.
“Xtensa: A Configurable and Extensible Processor”; Gonzalez; 2000; IEEE.
“OneChip: An FPGA Processor With Reconfigurable Logic”; Wittig et al.; 1996; IEEE.
Hauser, John R. et al., “Garp: A MIPS Processor with a Reconfigurable Coprocessor”, 5th Annual IEEE Symposium, Apr. 16-18, 1997, pp. 24-33, available from IEEE, 3 Park Avenue, 17th Floor, New York, NY 10016-5997.
Wittig, Ralph D. et al. “OneChip: An FPGA Processor With Reconfigurable Logic”, 1996, pp. 126-135, available from IEEE, 3 Park Avenue, 17th Floor, New York 10016-5997.
U.S. Appl. No. 10/912,844, filed Aug. 6, 2004, Ansari et al.
U.S. Appl. No. 10/912,865, filed Aug. 6, 2004, Purcell et al.
U.S. Appl. No. 10/913,231, filed Aug. 6, 2004, Ansari et al.
U.S. Appl. No. 10/913,282, filed Aug. 6, 2004, Ansari et al.
U.S. Appl. No. 10/913,991, filed Aug. 6, 2004, Purcell et al.
QinetiQ: Data Sheet—Preliminary; “Quixilica Floating-Point Unit for PPC405 Core with Optimised Vector Maths Library”; NASoftware Limited; QINETIQ/S&E/APC/TDS021842, Issue 2; pp. 1-4.
IBM; “Book E—Enhanced PowerPC Architecture”; Version 1.0;May 7, 2002; pp. 1-438.
Xilinx, Inc.; “The Programmable Logic Data Book 2000”; Published Apr. 2000; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 3-75 through 3-96.
Xilinx, Inc.; “Virtex-II Platform FPGA Handbook”; published Dec. 2000; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 33-75.
Xilinx, Inc.; “Virtex-II Pro Platform FPGA Handbook”; published Oct. 14, 2002; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 19-71.

Affiliated with

Also associated with

Rating

Decoder interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Decoder interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Decoder interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3905058