Decoder for single cycle decoding of single prefixes in variable

Details Decoder for single cycle decoding of single prefixes in variable Decoder for single cycle decoding of single prefixes in variable

1994-03-01

1996-07-16

Lim, Krisna

Boots, shoes, and leggings

3642553, 3642599, 36426281, G06F 930

Patent

active

055376290

ABSTRACT:
A prefix decoder for decoding a plurality of prefixes of a variable length instruction code, in order to supply multiple prefix vectors to a multiple instruction decoder without incurring a one clock penalty. The parallel prefix decoder includes a plurality of prefix decoders, each coupled to receive an instruction byte from an instruction buffer, and in response thereto to supply a prefix vector that includes coded prefix information in a format that is easy to use by subsequent decoder logic. A multiplexer receives the plurality of prefix vectors, and if a steered macroinstruction has a single prefix byte, then a control circuit selects the prefix vector to supply to the macroinstruction decoder. If multiple macroinstructions are steered to multiple macroinstruction decoders, then a prefix vector can be supplied to each decoder.

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