Decoder for memory data bus

Details Decoder for memory data bus Decoder for memory data bus

2006-12-12

2006-12-12

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

C365S230030, C365S230080

Reexamination Certificate

active

07149143

ABSTRACT:
Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines from the selected column page before the currently latched values have been read out. A specialized decoder and a latch control circuit allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or in multiplexing the sense amplifiers. The design allows there to be no gaps or latencies while reading data from the memory due to reloading the read latches or multiplexing the sense amplifiers to sense a following set of data bit lines.

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