Decoder for digital TV receiver

Details Decoder for digital TV receiver Decoder for digital TV receiver

1999-04-29

2001-12-25

Kelley, Chris (Department: 2613)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C382S232000, C382S239000, C382S240000

Reexamination Certificate

active

06333952

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a decoder for a digital TV receiver and more particularly for a digital TV to improve the picture quality of a video when a Standard Definition class TV receiver receives a High Definition class video signal.
2. Background of the Related Art
Generally, a digital TV receiver receives and decodes a video signal compressed in the MPEG
2
format at a decoder to display the video on a screen. Depending upon the number of picture elements (pels) in relation to the resolution and image reproductivity or picture quality, a digital TV supports two classes of video signals, namely the High Definition TV (HDTV) and the Standard Definition TV (SDTV). The HDTV class video signal has a maximum capability of 1920 pels/1080 lines and the SDTV class video has a capability of 704 pels/480 lines. For purposes of explanation, the capability will be limited to a HDTV class signal of 1920 pels/1080 lines and a SDTV class signal of 720 pels/480 lines.
A conventional decoder for a digital TV receiver will be explained with reference to the figures. A widely used format is a ratio of three components of luminance information Y and chrominance information Cb and Cr in a horizontal (or scanning) line on a TV screen or the like, represented as 0:0:0.
FIG. 1A
shows a 4:4:4 video format,
FIG. 1B
shows a 4:2:2 video format, and
FIG. 1C
shows a 4:2:0 video format. In the figures, the cross represents a luminance signal Y and the circle represents a chrominance signal Cb or Cr.
Particularly, the luminance indicates the extent of brightness of an image and the luminance of a pel is represented with 8 bits according to the ITU-R BT.601 recommendation. The chrominance or color difference is the information on a color of an image and is also represented by 8 bits according to the ITU-R BT.601 recommendation. Thus, a total of 24 bits are assigned to one pel. However, because the human eye is not very sensitive to the small variations in color, some color information is frequently left out in the representation of the video.
Particularly,
FIG. 1A
shows the video format 4:4:4 in which no color information is left out.
FIG. 1B
shows the video format 4:2:2 in which half of the color information in a horizontal direction is left out.
FIG. 1C
shows the video format 4:2:0 in which half of the color information in both the horizontal and vertical direction is left out. Namely, the 4:2:2 format has color information which is half of luminance information, and the 4:2:0 format has color information which is quarter of luminance information.
In a digital TV receiver, one digital pel is typically expressed by 8 bits and every macro block has 16×16 pel data. The decoder processes a bit stream corresponding to each class inclusive of Discrete Cosine Transform (DCT) coefficients and motion vector information.
FIG. 2
shows a block diagram of a conventional decoder for a digital TV receiver including a Variable Length Decoder (VLD)
1
for variable length decoding of a received bit stream data to provide DCT coefficients and motion vectors; an Inverse DCT (IDCT)
2
for inverse discrete cosine transforming the DCT coefficients to decode the DCT coefficients into spatial pel values; an adder
3
for adding data motion compensated at a motion compensated predictor
4
to the decoded data, to restore a video data; a frame memory
5
for storing the restored video data in a 4:2:0 video format; and an upsampling unit
6
for upsampling the data stored in the frame memory
5
into a 4:2:2 video format to output the video to a display unit. The motion compensated predictor
4
compensates the video data stored in the frame memory
5
using the motion vectors from the VLD
1
, and forwards the compensated data to the adder
3
.
Having a capability to receive and decode a HD class video data, a HD class digital TV receiver has no problems receiving and decoding a SD class video data. However, a SD class digital TV which is adapted to receive and decode a SD class video data cannot receive and decode a HD class video data. Nevertheless, in order to achieve full compatibility, the SD class digital TV receiver should also have the capability to receive and process the HD class video class. Thus, a decoder for the SD class digital TV receiver has been adapted to carry out a SD class data processing on a HD class data by a process known as down-converting, which is essentially a down sampling or filtering/decimation.
FIG. 3
shows one example of a decoder in the related art for a SD class TV receiver to carry out the down-converting process by receiving, decoding and displaying a HD class data. In
FIG. 3
, an 8×8 block data is decoded by reducing the data into a 4×4 block data. An 8×8 block data
41
is inverse discrete cosine transformed and downsampled in the horizontal and vertical directions at an IDCT/down-sampling unit
42
for 8 pels to reduce the 8×8 block into a 4×4 block. Particularly, 16 coefficients, indicated as black dots in the data block
41
, are selected from the upper left hand corner and subjected to the IDCT to obtain a down-sampled video data. The remaining coefficients, indicated as white dots are discarded. There are numerous other ways in selecting the coefficients.
In
FIG. 3
, the 4×4 down sampled video data is added to the motion compensated data at an adder
43
and stored in a frame memory
44
(or field memory). In order to process motion vectors corresponding to the down-sampled video data, the video data in the frame memory
44
is upsampled in horizontal/vertical directions at an upsampling unit
45
to an 8×8 data. The upsampled video data is motion compensated by the motion vectors at a motion compensated predictor
46
, downsampled in horizontal/vertical directions at a downsampling unit
47
back to a4×4 data, and added to the adder
43
to obtain a video block downsampled from 8×8 data to 4×4 data. The downsampled video data in finally stored in the frame memory. To present the data, the data from the frame memory
44
is converted into the 4:2:0 format at a format converter
48
and converted into the 4:2:2 format at an upsampling unit
49
before presentation.
FIG. 4
shows another example of a decoder in the related art for a SD class TV receiver to carry out the down-converting process by receiving, decoding and displaying a HD class data. In
FIG. 4
, an 8×8 block data is decoded by reducing the data into an 8×4 block data. An 8×8 block data
51
is inverse discrete cosine transformed and downsampled in the horizontal and vertical directions at an IDCT/down-sampling unit
52
for 8 pels to reduce the 8×8 block into a 8×4 block. Similarly to
FIG. 3
, after selecting
32
coefficients from the left hand side, indicated as black dots in the data block
41
, the remaining coefficients, indicated as white dots are discarded. There are also numerous other ways in selecting the coefficients.
In
FIG. 4
, the 8×4 down sampled video data is added to the motion compensated data at an adder
53
and stored in a frame memory
54
(or field memory). In order to process motion vectors corresponding to the down-sampled video data, the video data in the frame memory
54
is upsampled in horizontal/vertical directions at an upsampling unit
55
to an 8×8 data. The upsampled video data is motion compensated by the motion vectors at a motion compensated predictor
56
, downsampled in horizontal/vertical directions at a downsampling unit
57
back to an 8×4 data, and added to the adder
53
to obtain a video block downsampled from 8×8 data to 8×4 data. The downsampled video data in finally stored in the frame memory. To present the data, the data from the frame memory
54
is converted into the 4:2:0 format at a format converter
58
and converted into the 4:2:2 format at an upsampling unit
59
before presentation.
FIG. 5
shows yet another example of a decoder in the related art for an SD clas

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